Transport or Store?

Abstract

Flow-based microfluidic biochips have attracted much attention in the EDA community due to their miniaturized size and execution efficiency. Previous research, however, still follows the traditional computing model with a dedicated storage unit, which actually becomes a bottleneck of the performance of biochips. In this paper, we propose the first architectural synthesis framework considering distributed storage constructed temporarily from transportation channels to cache fluid samples. Since distributed storage can be accessed more efficiently than a dedicated storage unit and channels can switch between the roles of transportation and storage easily, biochips with this distributed computing architecture can achieve a higher execution efficiency even with fewer resources. Experimental results confirm that the execution efficiency of a bioassay can be improved by up to 28% while the number of valves in the biochip can be reduced effectively.

VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips

“…The second modification rule indicates that a chip component without valid flow channel connection is invalid. Thus, as an endpoint of the unavailable edge (12,14), vertex 14 is specified as unavailable, as shown in Figure 5(c).…”

“…The fourth modification rule indicates that a valid flow path must include an inlet and an outlet to ensure proper pressure drop. As a (8,10), (10,12), (12,14), (2,4),(4,5), (5,6),(9,10)} By recursively applying the modification rules until no more vertex or edge can be specified as unavailable, we can locate a valid flow path, as shown in Figure 5(f).…”

“…With a decade of effort, researchers have achieved significant progress covering both high-level synthesis and physical design. Specifically, up to 2019, there have been: high-level modeling methods that optimize the resource utilization based on given application protocols [4] [5]; place-and-route tools that synthesize manufacturing-ready physical designs targeting applications of different scales [6] [7] [8], scheduling and fluid routing approaches that map operations to given physical topologies [9] [10], and other frameworks focusing on specific optimization criteria such as fluid storage [11] [12] and control pin reduction [13] [14], etc.…”

Architectural Synthesis of Continuous-Flow Microfluidic Biochips with Connection Pair Optimization

“…On the other hand, ref. [19] pioneered an approach that prioritizes storage minimization as the objective during highlevel synthesis. Their aim was to enhance chip efficiency and decrease the execution time of bioassays; they formulated the binding and scheduling tasks using mathematical formulas.…”

“…A complete transportation path is required for a fluid transportation task, which also needs to be assigned a port and then scheduled for the task (lines [18][19][20][21]. This paper selects the minimum cost port and component interface through the connection to form a complete transportation path using the cost function CostC (calculated as in Formula (3)).…”