Trap Recovery by in-Situ Annealing in Fully-Depleted MOSFET With Active Silicide Resistor

Amor, Sarra Ben; Kilchytska, Valeriya; Flandre, Denis; Galy, Philippe

doi:10.1109/led.2021.3079244

Cited by 11 publications

(7 citation statements)

References 16 publications

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“…Such discrepancies should be properly addressed by considering VBE. [34,35] The need to introduce VBE is explained as follows. The difference in the current density between the FTJs on n-and p-Si is only %10 times that of the HRS.…”

Section: Electrical Properties Of Ferroelectric Tunnel Junctions On N...mentioning

confidence: 99%

“…[32] In fieldeffect transistors (FETs), the defect inside the gate oxide is known to generate the LFN by inducing carrier number fluctuation. [33][34][35][36] In semiconducting resistors or metals, however, carrier mobility fluctuated by the defect in the conduction path generates 1/f noise. [37][38][39] 1/f noise limits the performance, reliability, and survivability of semiconductor devices.…”

Section: Doi: 101002/aisy202200377mentioning

confidence: 99%

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1/f Noise in Synaptic Ferroelectric Tunnel Junction: Impact on Convolutional Neural Network

Shin

Min

Bae

et al. 2023

Advanced Intelligent Systems

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Conventional von Neumann architecture employs a physically distinct processor and memory. This results in considerable delay and energy costs, which is referred to as the von Neumann bottleneck. [1][2][3] Additionally, the memory wall, that is, the performance difference between memory and processing units, is continuously increasing and has become a key concern in the Internet of Things era. Therefore, a novel method of in-memory computing called neuromorphic computing was introduced, which allows concurrent logic and memory operations. [4][5][6] By combining logic and memory functionalities, neuromorphic computing can prevent frequent, time-consuming data transfers and thus significantly reduce power consumption.Neuromorphic computing requires synaptic devices with low-power consumption, multilevel conductance, high switching speeds, and small sizes. [7][8][9][10][11][12][13][14][15][16] In this regard, memristor devices, whose resistance states can be modified using electrical voltages, are promising candidates for synaptic devices, including resistive memristors, [7][8][9][10] magnetic tunnel junctions, [11][12][13] and phase-change memristors. [14][15][16] Recently, ferroelectric tunnel junctions (FTJs) have attracted considerable research attention as candidates for memristor devices in neuromorphic computing. [17][18][19] Under an applied voltage, the polarization of collectively ordered electrical dipoles in ferroelectric materials can be switched, resulting in a change in tunnel electroresistance (TER). Since the discovery of ferroelectricity in HfO 2 -based thin films in 2011, FTJs employing HfO 2 -based ferroelectric materials have piqued the interest of researchers owing to their compatibility with CMOS technologies. [20] In addition, FTJs have advantages of low-power operation, high access speeds, excellent scalability, and good durability. Accordingly, extensive efforts have been directed toward improving the performance of FTJs. The structure of an FTJ has evolved from metal-ferroelectric-metal to metal-ferroelectric-insulator-metal and metal-ferroelectric-insulator-semiconductor (MFIS) stacks as the asymmetric barrier potential profile between the top and bottom electrodes increases the TER ratio. [21,22] Numerous studies have indicated that the remnant polarization in FTJs can be improved by optimizing the fabrication parameters, such as the rapid thermal annealing (RTA) temperature, [23] thickness of the

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Section: Electrical Properties Of Ferroelectric Tunnel Junctions On N...mentioning

confidence: 99%

Section: Doi: 101002/aisy202200377mentioning

confidence: 99%

1/f Noise in Synaptic Ferroelectric Tunnel Junction: Impact on Convolutional Neural Network

Shin

Min

Bae

et al. 2023

Advanced Intelligent Systems

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“…Discovered a workable way to extend device scalability. Amor et al [22] demonstrated the use of electro-thermal annealing to improve the performance of FDSOI. Up to a temperature of 590 K, an improvement in SS and Id can be seen.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

2023

IJATEE

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The conventional silicon channel metal oxide semiconductor field effect transistor (MOSFET) has fundamental limits that are reached due to scalability, resulting in short-channel effects (SCE) and other issues in small-channel devices. To overcome these challenges and design a nanoscale device, an alternate material was needed. Graphene, a novel material with exceptional properties, has been utilized to create a graphene field-effect transistor (GFET) optimized using siliconon-insulator (SOI) technology. The SOI structure uses graphene as a channel, resulting in the development of a new silicon-on-insulator graphene field effect transistor (SIGFET) with an 18 nm channel length. The designed SIGFET exhibits significant improvements compared to traditional GFET and MOSFET. Specifically, the subthreshold slope (SS) of the SIGFET is 60.93 mV/decade, the drain-induced barrier lowering (DIBL) is 42.89 mV/V, and the ION/IOFF ratio is 6.55×108, which surpasses previous GFET-based contributions and SOI-MOSFET. Moreover, the effect of temperature change on SIGFET performance has been investigated, revealing that temperature variation only affects the drain current and has no impact on short channel characteristics. Therefore, the SIGFET can be an ideal substitute for traditional silicon channel devices.

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“…Besides, the LFN measurements can evaluate the defect states in the devices and the device reliability [15,16]. Several studies into the behavior and origins of LFN in Si-based [22] and GaAs/InP-based cryogenic systems [5,23] have been conducted. Nevertheless, there are few studies into the LFN characteristics of GaN HEMTs in the cryogenic environment, especially at extremely low temperatures down to 4.2 K.…”

Section: Introductionmentioning

confidence: 99%

DC and low-frequency noise characteristics of GaN-based HEMTs under cryogenic temperatures

Zeng¹,

Zhang²,

Luo³

et al. 2022

J. Phys. D: Appl. Phys.

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In this work, the device characteristics of GaN-based high-electron-mobility transistors (HEMTs) were systematically investigated by the direct current (DC) and low-frequency noise (LFN) measurements within the temperature ranging from 300 K to 4.2 K. The temperature-dependent behavior of the on- and off-state electrical properties was statistically analyzed, highlighting an overall improved device performance under the cryogenic temperatures. In addition, the LFN of the device exhibited an evident behavior of 1/f noise from 10 Hz to 10 kHz in the measured temperature range and can be well described by the carrier number fluctuations with correlated mobility fluctuations (CNF/CMF) model down to 4.2 K. Based on this model, we further extracted and discussed the defect-related behavior in the devices under low-temperature environments. These experimental results provide insights into the device characteristics of GaN-based HEMTs under cryogenic environments, motivating further studies into the GaN-based cryo-devices and systems.

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Trap Recovery by in-Situ Annealing in Fully-Depleted MOSFET With Active Silicide Resistor

Cited by 11 publications

References 16 publications

1/f Noise in Synaptic Ferroelectric Tunnel Junction: Impact on Convolutional Neural Network

1/f Noise in Synaptic Ferroelectric Tunnel Junction: Impact on Convolutional Neural Network

Design of silicon-on-insulator field-effect transistor using graphene channel to improve short channel effects over conventional devices

DC and low-frequency noise characteristics of GaN-based HEMTs under cryogenic temperatures

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