Trap states in InAlN/AlN/GaN-based double-channel high electron mobility transistors

Abstract

We present a detailed analysis of trap states in InAlN/AlN/GaN double-channel high electron mobility transistors grown by pulsed metal organic chemical vapor deposition. By frequency dependent conductance measurements, trap densities and time constants at both InAlN/AlN/GaN interfaces were determined. Two types of traps, with a high density of up to ∼1014 cm−2 eV−1, were observed existing at the higher InAlN/AlN/GaN interface. On the other hand, the density dramatically decreased to ∼1012 cm−2 eV−1 for traps located at lower InAlN/AlN/GaN interface on which a low-temperature grown GaN (LT-GaN) layer was deposited. Additionally, photo-assisted capacitance-voltage measurements were performed to estimate deep-level defects, yielding a low density of 1.79 × 1011 cm−2 acting as negative fixed charges at the LT-GaN and lower InAlN interface.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

“…Curve (1) was the initial downward sweep, curve (2) followed in the same direction, and curve (3) was a final upward sweep. A clear deviation is seen between curve (1) and subsequent curves that may amount to charging of interface and bulk traps in the hetero-system [22], [26]. The curve evolution from (2) to (3) shows some hysteresis, which may indicate oxide or confined mobile charge in the GaN spacer layer or buffer layer.…”

“…A notable result of the recessed-gate HEMT is that after the GLR sequence was stopped and restarted, the initial drain current density had not diminished despite the absence of a passivation layer other than the thin Al 2 O 3 gate insulation. Although other reports have been made on nitride-based dualchannel HEMTs with alloyed barrier layers [20], [21], [22], none have included gate lag measurements. To the best of our knowledge, this is the first report on dual-channel AlN/GaN HEMT gate lag as well as its innovation to the recessed-gate HEMT architecture.…”

“…Therefore, purely dual-channel AlN/GaN/AlN/GaN HEMTs have also been fabricated on the same wafer, serving as both a calibration structure for CV and IV characterization as well as a proxy to the recessed-gate HEMT access region. Several reports have been made on nitride-based dual-channel HEMTs with AlGaN or AlInN barriers with the intent to increase drain current density or assess HEMT noise characteristics and subsequently disregarded gate lag performance [20], [21], [22]. A notable attribute of using the AlN/GaN heterostructure for the HEMT design reported in this work is that the AlN barrier layers are inherently thin (< 5 nm), which allows extremely shallow channels and therefore, multiple channel designs to maintain channels in close proximity to the surface.…”

Polarization-mediated Debye-screening of surface potential fluctuations in dual-channel AlN/GaN high electron mobility transistors

“…1. 43 , 38 The recessed-gate HEMT showed an emphasized (dis)charge curvature of the drain current pulse in Fig. 10(b).…”

“…Several reports have been made on nitride-based dual-channel HEMTs with AlGaN or AlInN barriers with the intent to increase drain current density or assess HEMT noise characteristics and subsequently disregarded pulsed-gate and large-signal performance. [41][42][43] A notable attribute of using the AlN/GaN heterostructure for the HEMT design reported in this work is that the AlN barrier layers are inherently thin (< 5 nm), which allows extremely shallow channels and therefore, multiple channel designs to maintain channels in close proximity to the surface as a means to boost drain current density without sacrificing gate charge control. This is not the case for ternary barriers that require a sufficient thickness in order to induce 2DEG…”