Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure

Lamech, Charles; Plusquellic, Jim

doi:10.1109/hst.2012.6224324

Cited by 29 publications

(12 citation statements)

References 8 publications

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“…Specifically, we do not address the case of HTcaused information leakage via a side-channel such as energy consumption. A variety of approaches address HT-induced by side-channel leakage has been published in a recent survey paper; see Bhunia et al [4] and others [11][12].…”

Section: Relationship To Other Threat Scenariosmentioning

confidence: 99%

A signature based architecture for Trojan detection

Gbade-Alabi

Keezer

Mooney

et al. 2014

Proceedings of the 9th Workshop on Embedded Systems Security

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Trust in the integrated circuit (IC) fabrication industry is an ongoing concern given the trend towards "fabless" design and associated use of third-parties for fabrication. A Hardware Trojan (HT) introduced during fabrication can corrupt an IC's outputs, leak secret information, and yet go undetected by traditional system testing techniques. In this paper we propose an architecture to detect HTs during IC test or at run-time. An HT that would corrupt an IC's output and otherwise proceed undetected will then be rendered useless by this architecture. This approach will therefore discourage the insertion of HTs in the first place. The proposed architecture takes encryption hardware as a paradigmatic casestudy and uses digital "signatures" derived from the plaintext to identify if the ciphertext has been corrupted by HTs. We test this methodology through simulation on various types of HTs inserted into a lightweight cryptographic system called "PRESENT" [13]. Our results validate that activated HTs are detected by this methodology.

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Section: Relationship To Other Threat Scenariosmentioning

confidence: 99%

A signature based architecture for Trojan detection

Gbade-Alabi

Keezer

Mooney

et al. 2014

Proceedings of the 9th Workshop on Embedded Systems Security

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“…In [27], a transparent mode is introduced in a design with a FSM to enhance the controllability and observability of internal nodes. Researchers have also shown that high-precision delay structure or current sensing circuit can be embedded into a design to improve HT detectability [28], [29]. Functional filler cells are inserted into unused space to prevent HT insertion [30].…”

Section: A Related Workmentioning

confidence: 99%

SeMIA: Self-Similarity-Based IC Integrity Analysis

Zheng

Yang

Bhunia

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Counterfeit chips in the supply chain as well as hardware Trojan attacks pose serious threats to the semiconductor industry. If undetected before deployment, they can lead to serious consequences including system performance/reliability issues during field operation and potential revenue/reputation loss for a trusted manufacturer. Currently, no unified detection method is available that can simultaneously address these integrity violations in integrated circuits (ICs). In addition, most existing detection approaches require a set of golden chips as a reference, which significantly increases the test cost and complexity. Furthermore, in some scenarios, it may be extremely difficult to obtain golden chips. In this paper, we present a novel unified IC integrity analysis approach that can effectively detect both recycled counterfeit ICs (the most dominant form of counterfeiting) as well as Trojan attacks in ICs without the need of golden chips. The proposed approach, referred to as SeMIA, exploits intrinsic structural self-similarity in a design (e.g., multiple cores, multiple functional units of the same type, different parts of an adder) to isolate recycled chips and hardware Trojan attacks under large inter-and intra-die process variations. It compares dynamic current (IDDT ) signatures between two adjacent similar circuit structures using an appropriate isolation metric to detect such attacks with high degree of confidence. SeMIA does not rely on any embedded structure for authentication, thus it comes at virtually zero hardware overhead and can be applied to chips already produced. Through extensive simulations, we show that for 15% inter-and 10% intra-die variations in threshold voltage for a 45nm CMOS process, over 98% of recycled chips can be reliably identified. Finally, experimental measurements on Field Programmable Gate Array (FPGA) chips demonstrate the effectiveness of SeMIA for protection against both attacks.

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“…Several techniques recommended designfor-hardware-trust aimed to magnify Trojan impact during authentication [7][8] [9]. Further, several side-channel-based techniques have been introduced to distinguish the contribution of Trojans from the impact of process variations in a circuit [10] [11][12] [13]. Hardware Trojan design and implementation were presented in [14][15] [16] [17].…”

Section: Introductionmentioning

confidence: 99%

Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level

Salmani

Tehranipoor

2013

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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Considerable attention has been paid to hardware Trojan detection and prevention. However, there is no existing systematic approach to investigate circuit vulnerability to hardware Trojan insertion during development. We present such an approach to investigate circuit vulnerability to Trojan insertion at the behavioral level. This novel vulnerability analysis determines a circuit's susceptibility to Trojan insertion based on statement hardness analysis as well as observability of circuit signals. Further, the Trojan detectability metric is introduced to quantitatively compare the detectability of behavioral Trojans inserted into different circuits. This creates a fair comparison for analyzing the strengths and weaknesses of Trojan detection techniques as well as helping verify trustworthiness of a third party Intellectual Property (IP).

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Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure

Cited by 29 publications

References 8 publications

A signature based architecture for Trojan detection

A signature based architecture for Trojan detection

SeMIA: Self-Similarity-Based IC Integrity Analysis

Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level

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