TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects

Dang, Khanh N.; Ahmed, Akram Ben; Abdallah, Abderazek Ben; Tran, Xuan‐Tu

doi:10.1109/isvlsi.2019.00096

Cited by 9 publications

(17 citation statements)

References 32 publications

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“…However, reducing the test period (time between two consecutive tests) can significantly reduce the system performance. In [40], [41], the authors proposed a method to test TSVs without any interruption or degradation of the system performance. The major drawback of these non-degradation tests is the long execution time.…”

Section: Related Workmentioning

confidence: 99%

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A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

et al. 2020

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As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Networkon-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles). INDEX TERMS 3D-ICs, fault-tolerance, error correction code, through-silicon-via, product code, parity check, networks-on-chip, fault-detection.

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Section: Related Workmentioning

confidence: 99%

“…Nevertheless, our method is the best in terms of detectability and testing time. Moreover, we can use our method to provide a calling mechanism for BIST, which can localize and extract the positions of faults by using deferred testing [40], [41].…”

Section: Comparison Of Network-on-chip Testingmentioning

confidence: 99%

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

et al. 2020

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“…Motivated by the above problems, TSV-based 3D-ICs desire to have a method to monitor, detect, localize, and recover from TSV defects. In [27], an on-communication test (OCT) method was previously presented by testing the communication medium along with its operations. The main idea in the aforementioned work is to use Error Correction/Detection Code as the baseline and improve its detectability and correctability using augmented algorithms.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we propose a novel method named Isolation and Shift in Group (IaSiG), which is not only an OCT method, it also provides recovery right after its execution. This work is based on our preliminary work in [27] 1 with the additional new contributions as follows:…”

Section: Introductionmentioning

confidence: 99%

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A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

et al. 2020

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Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R + 1 defects. Moreover, by using G groups, it can localize up to G × R and detect up to G × (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

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2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults

Dang

Meyer

Ahmed

et al. 2019

2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects

Cited by 9 publications

References 32 publications

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults

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