2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International 2012
DOI: 10.1109/3dic.2012.6262947
|View full text |Cite
|
Sign up to set email alerts
|

TSV optimization for BEOL interconnection in logic process

Abstract: Control of Cu extrusion and delamination due to CTE mismatch between Si and Cu is a big issue for high reliable TSV formation. In this paper we tried to find some methods to reduce Cu extrusion and to prevent TSV sidewall delamination. It is demonstrated that residual Cu extrusion height can be reduced by additional high temperature heat treatment before TSV CMP. And also Cu extrusion and delamination strongly depends on TSV dimension, which leads to the conclusion that smaller vias are preferred for better re… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2013
2013
2020
2020

Publication Types

Select...
5
1

Relationship

0
6

Authors

Journals

citations
Cited by 9 publications
(1 citation statement)
references
References 1 publication
0
1
0
Order By: Relevance
“…ICs are often the primary source of radiated emissions, and near field magnetic field can help engineers to track down EMI culprit and solve the . Three-dimensional stack-dies integrated circuits (3D-ICs) trend for vertical distance between ICs [16][17][18][19][20][21][22][23].…”
Section: Introductionmentioning
confidence: 99%
“…ICs are often the primary source of radiated emissions, and near field magnetic field can help engineers to track down EMI culprit and solve the . Three-dimensional stack-dies integrated circuits (3D-ICs) trend for vertical distance between ICs [16][17][18][19][20][21][22][23].…”
Section: Introductionmentioning
confidence: 99%