Tunable Level-Shifter / Buffer for Dual Supply Systems and Low-Power Clock-tree Design in Deep-Submicron Application

Abstract

A new architecture for Analog tunable level-shifter is introduced in the 1 30nm CMOS process. As the transistor keeps on shrinking, low power design becomes more challenging. Dual supplies are used for many low-power applications and needs level-shifter between the low Vdd and High Vdd critical path. Similarly, although the die sizes are shrinking but the high speed VOs are relatively larger and hence use higher Vdd supply, and hence needs level-shifters in between the core and the /O circuits. Also the clock trees are major source for power dissipation in present day high-speed design. Reducing the clock swings within the tree and the branches can help reduce the overall power dissipation for the chip. The new tunable -Level shifter takes in different input voltages and shifts it to 1.2V-I.5V outputs. The input voltage can range from 0.45V to Vdd, while the threshold for the shifter is tuned using a referencevoltage, thus controlling the current through the levelshifter/buffer. Modification has been done to the circuit for low-power application with minimal degradation to the performance.

Stochastically Estimating Modular Criticality in Large-Scale Logic Circuits Using Sparsity Regularization and Compressive Sensing

“…In fact, many innovative low-power circuit design methods have been developed to exploit the concept of logic criticality. For example, dual supplies [21] are used for many low-power applications and need level-shifters between the low V DD and high V DD critical path. However, when V DD is lowered, the reliability and circuit performance become challenging issues.…”