Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

Alper, Cem; Michielis, L. De; Daǧtekın, Nilay; Lattanzio, Livio; Ionescu, Adrian M.

doi:10.1109/essderc.2012.6343358

Cited by 12 publications

(13 citation statements)

References 11 publications

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“…Figure 8 clearly reveals the signature characteristics of TFET devices, C gd is higher than C gs. In contrast, C gs is higher than C gd for MOSFET, which is in accordance with the findings of Yang et al [16], known as on-state Miller capacitance effect. For TFETs, C gd increases with V GS because of the decrease in the drain-to-channel potential barrier, and C gs remains almost unaffected with increase in the gate bias.…”

Section: Analog Performance Investigationsupporting

confidence: 92%

“…TFET exhibits higher output resistance than corresponding MOSFET structure owing to its less channel‐length modulation and excellent current saturation behavior . This results correlates well with the previously published result by Alter et al . A higher output resistance is desirable in order to obtain higher intrinsic gain.…”

Section: Analog Performance Investigationsupporting

confidence: 89%

“…It is because of the fact that TFET employs a complete different mechanism of carrier injection based on BTBT than a MOSFET which allows it to overcome 60 mv/dec subthreshold slope limit. 19 cm À3 Doping level of the drain (n + ) 5x10 19 cm À3 Doping level of the channel (n À for TFET and p À for MOSFET) 5x10 16 cm À3 Workfunction of the gate electrode 4.61 eV Length of the underlap 0 nm…”

Section: Resultsmentioning

confidence: 99%

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Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET

Baral¹,

Biswal²,

et al. 2016

Int J Numerical Modelling

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Summary In this paper, the analog/radio frequency (RF) and linearity performance of an InAs‐based nanowire (NW) tunnel field‐effect transistor (TFET) is studied and compared with InAs‐based NW MSFET of identical dimension. InAs‐based NW TFETs shows a great promise for high performance digital application because of its superior subthreshold behavior. Different analog/RF and linearity key figure‐of‐merits like cut‐off frequency (ft) and 1‐dB compression point are extracted and the effect of gate length down scaling on those parameters has been studied. The results reveal that down scaled InAs‐based NW TFET shows a significant improvement in its RF and linearity performance. However, this advantage diminishes in terms of poor analog performance with gate‐length downscaling. This clearly indicates the necessity of a trade‐off between analog and RF performance. Moreover, an in‐depth comparison between InAs‐based NW TFET and conventional MOSFET has also been provided in order to demonstrate the superiority of InAs‐based NW TFET to become a competitive contender by replacing conventional MOSFET for Analog/Mixed signal System‐on‐Chip (SOC) applications. Copyright © 2016 John Wiley & Sons, Ltd.

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Section: Analog Performance Investigationsupporting

confidence: 92%

Section: Analog Performance Investigationsupporting

confidence: 89%

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET

Baral¹,

Biswal²,

et al. 2016

Int J Numerical Modelling

View full text Add to dashboard Cite

show abstract

“…It is the same as previous result that two capacitors are connected in parallel. At a fixed DS , the trends of the gs and gd coincide with the foregoing discussion [17,18]. It is also shown from the capacitance-voltage characteristics at GT = 0.4 V and 0.6 V in Figure 5(b) that gd rapidly decreases for further increase at DS = 0.6 V. Meanwhile, the gs reaches saturation, due to the reduction in the tunnel barrier width for further DS ; the source depletion width also weakly depends on the drain voltage.…”

Section: Analysis Of Gate-to-source Capacitance and Gate-to-supporting

confidence: 84%

Drive Current Enhancement in TFET by Dual Source Region

Zhi

Zhang

Liu

et al. 2015

Journal of Electrical and Computer Engineering

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This paper presents tunneling field-effect transistor (TFET) with dual source regions. It explores the physics of drive current enhancement. The novel approach of dual source provides an effective technique for enhancing the drive current. It is found that this structure can offer four tunneling junctions by increasing a source region. Meanwhile, the dual source structure does not influence the excellent features of threshold slope (SS) of TFET. The number of the electrons and holes would be doubled by going through the tunneling junctions on the original basis. The overlap length of gate-source is also studied. The dependence of gate-drain capacitanceCgdand gate-source capacitanceCgson gate-to-source voltageVgsand drain-to-source voltageVdswas further investigated. There are simulation setups and methodology used for the dual source TFET (DS-TFET) assessment, including delay time, total energy per operation, and energy-delay product. It is confirmed that the proposed TFET has strong potentials for VLSI.

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“…The inclusion of various dielectric materials is proposed by simple fabrication steps in [25,26]. Changing k d affects the high frequency response efficiently.…”

Section: Improving High-frequency Performancementioning

confidence: 99%

Influence of gate overlap engineering on ambipolar and high frequency characteristics of tunnel-CNTFET

Shaker

Ossaimee

Zekry

et al. 2015

Superlattices and Microstructures

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Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

Cited by 12 publications

References 11 publications

Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET

Effect of gate‐length downscaling on the analog/RF and linearity performance of InAs‐based nanowire tunnel FET

Drive Current Enhancement in TFET by Dual Source Region

Influence of gate overlap engineering on ambipolar and high frequency characteristics of tunnel-CNTFET

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