Abstract. This paper describes and analyzes the security of a general-purpose cryptographic function design, with application in RFID tags and sensor networks. Based on these analyzes, we suggest minimum parameter values for the main components of this cryptographic function, called ARMADILLO. With fully serial architecture we obtain that 2 923 GE could perform one compression function computation within 176 clock cycles, consuming 44 µW at 1 MHz clock frequency. This could either authenticate a peer or hash 48 bits, or encrypt 128 bits on RFID tags. A better tradeoff would use 4 030 GE, 77 µW of power and 44 cycles for the same, to hash (resp. encrypt) at a rate of 1.1 Mbps (resp. 2.9 Mbps). As other tradeoffs are proposed, we show that ARMADILLO offers competitive performances for hashing relative to a fair Figure Of Merit (FOM).

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.

In this paper we analyze and discuss the characteristics and expected benefits of some emerging device categories for ultra low power integrated circuits. First, we focus on two categories of sub-thermal subthreshold swing switches Tunnel FETs and Negative Capacitance (NC) FETs and evaluate their potential advantages for digital and analog design, compared to CMOS. Second, we investigate the combined low power and novel integrated functionality in some hybrid Nano-Electro-Mechanical (NEM) devices: the Resonant Body (RB) Fin FET for nW time reference ICs and dense arrays of Suspended Body (SB) Double Gate (DG) Carbon Nanotube (CNT) FET for low power analog/RF and integrated sensor arrays.

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