Two Dimensional Analytical Subthreshold Model of Nanoscale Cylindrical Surrounding Gate MOSFET Including Impact of Localised Charges

Abstract

The paper presents a two dimensional analytical subthreshold model of Nanoscale Cylindrical Surrounding Gate (SRG) MOSFET with localised/fixed interface charges. The model is used to study the effect of localised charges induced at the semiconductor/oxide interface due to the hot carrier induced damage, stress induced damage or radiation induced damage on the electrical performance of the device. The device reliability issues of Nanoscale Cylindrical SRG MOSFETs under localised interface charges are also studied and effects of extension, position, density and polarity of interface localised charges are discussed in detail in terms of change in potential, threshold voltage shift, drain current degradation.

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

“…These localized charges are created either during the manufacturing process (stress-induced damage, radiation-induced damage) or by hot carriers, under high applied drain voltage near the drain-channel junction, giving rise to localized charge pile up of interface traps (N it ) near the drain-channel region [9]. In particular, these generated localized trap charges due to high electric field (leading to hot carrier generation) results in threshold voltage shift, and SS degradation by surpassing the barrier at the Si-SiO 2 interface and will disintegrate the original performance of the device and finally lead to permanent device failure [10,11]. Previously the hot carrier degradation (HCD) mechanism based on Si-Si, Si-O and Si-H bond breaking has been thoroughly studied [12][13][14].…”

Effect of ITC on the characteristics of junctionless nanowire transistor(JLNWT) for future ULSI applications: Semianalytical modeling approach

“…The amount of change in flat band voltage under the damaged region depends upon the density of interface trap charges and is given by [13], [18]: it is evident that the minimum central potential is increased /decreased with the positive and negative interface trap changes respectively. Thus the change in minimum central potential and its position induces a shift in the threshold voltage.…”

“…The coefficients A, B, C, D, d S and d D are the constants and can be obtained by using the continuity condition of potential and electric field (See the appendix A), given as; (18) and (19) are two quadratic coupled equations shows that the SCEs in the nano scaled devices due to variation in drain to source voltage, not only affects the drain depletion width but also some extent at the source side. In the present analysis, the value of d S and d D from the quadratic coupled equations (18) and (19) is calculated by using Newton-Raphson method.…”

“…The subthreshold current can be calculated by using potential distribution in the silicon film and is given as [18];…”

Surface Potential modeling of Dual Metal Gate-Graded Channel-Dual Oxide Thickness with two dielectric constant different of Surrounding Gate MOSFET

“…These new architectures must offer the advantage of better control of potential in the channel by the gate voltage what will make it possible to still push back the limits of the miniaturization of the MOSFETS. The structure Gate-All-Around MOSFET also called "surroundinggate MOSFET" [4], offers a better control of the electrostatic potential by appearing with DG MOSFET structure [5]. In recent years, to reduce the SCEs and improve hot carrier reliability, various studies have been carried out on SG MOSFET.…”