Two dimensionally inhomogeneous structure at gate electrode/gate insulator interface causing Fowler-Nordheim current deviation in nonvolatile memory

Ushiyama, M.; Ohji, Yuzuru; Nishimoto, T.; Komori, Kazuhiro; Murakoshi, H.; Kume, Haruki; Tachi, S.

doi:10.1109/relphy.1991.146039

Cited by 13 publications

(1 citation statement)

References 12 publications

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“…11). As a result, a local electric field enhancement due to the segregation is suppressed, the effective barrier height for conductive carriers is increased, and the gate leak current is reduced 17,18) (Fig. 12).…”

Section: Device Characteristicsmentioning

confidence: 99%

Novel Laser Annealing Process for Advanced Complementary Metal Oxide Semiconductor Devices with Suppressed Polycrystalline Silicon Gate Depletion and Ultra shallow Junctions

Shima¹,

Mine²,

Torii³

2007

jjap

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One of the major challenges in advanced complementary metal oxide semiconductor (CMOS) technology is to achieve an adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. We investigated gate pre annealing by laser thermal process (LTP) in conjunction with laser spike annealing (LSA) source/drain (S/D) activation to effectively suppress poly-Si gate depletion while forming highly activated ultra shallow junctions for S/D. We found that carrier concentration at the poly-Si gate/gate oxide interface increases and, accordingly, electrical inversion oxide thickness (Tinv) decreases whereas dopant penetration into the Si substrate is suppressed to a level far below that in conventional rapid thermal annealing (RTA). We realized improved device performance characteristics such as a high drive current, a small threshold voltage (Vth) shift, and a reduced off current (Ioff).

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Section: Device Characteristicsmentioning

confidence: 99%