Two novel low power and very high speed pulse triggered flip‐flops

Summary In this paper, an asynchronous digital circuit is introduced for increasing the amount of delay in binary delay lines in an area efficient way. The circuit that uses its slave delay line twice per delay event is called asynchronous delay doubler (ADD). The delay increases exponentially, while the number of components increases linearly in the recursive utilization of ADD. An assumption on the event interval of the input 2signal helps to design the ADD in a very simple form. Therefore, the ADD can be implemented with a small amount of logical resource (gates or look‐up tables). For proper operation, interval between the events (positive edge or negative edge) on the binary input signal should be larger than the delay provided by the recursive ADD block. In order to satisfy this assumption, an auxiliary asynchronous circuit, which is called binary low‐pass filter (BLPF), is also proposed. The BLPF filters out the pulses narrower than the delay generated by its recursive ADD block. The proposed ADD design is suitable especially for the applications, like random number generation, in which the deviation in amount of delay is useful as an entropy source. In order to prove the concept, a chain of recursive ADD block is implemented with BLPFs on a field‐programmable gate array and utilized in a true random bit generator. Copyright © 2015 John Wiley & Sons, Ltd.

Section: Delaying Binary Signalsmentioning

confidence: 99%

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

Yeniceri

Yalçın

2015

“…The market of mobile phones and the field of internet of things both are increasing aggressively 1,2 . In addition to that, basic digital camera, tablet, laptop, advancement of different kinds of wearable information devices or health‐care devices are in huge demand 3,4 .…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application

Mishra

Vaithiyanathan

Chopra

2021

Summary This paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18 transistors with a single‐phase clock and mixed topology. This design has lowest complexity, so flip‐flop basically focuses on the performance issue such as delay (TCQ) and average power consumption and compared with the other existing logic structured flip‐flops. The proposed circuit is implemented at 65‐nm Complementary Metal‐Oxide Semiconductor (CMOS), and 18‐nm finFET technology node using cadence virtuoso. The proposed flip‐flop architecture have outperformed transmission gate flip‐flop (TGFF) in terms of power (i.e., 74.52%). It is also showing improvement in terms of power as compared to 18‐transistor single‐phase clocking (18TSPC). This work also enhances the speed by reducing the delay minimum of 11.28% and PDP minimum of 37.18%. By using adaptive pass transistors topology to construct flip‐flop, the total area of the proposed flip‐flop reduces by a minimum of 4.78% with respect to 18TSPC, and also with the other flip‐flops reported in this paper. The proposed circuit can work properly within the frequency range up to 2‐GHz clock frequency. Monte Carlo simulations of Power and C to Q delay have been performed for 1000 samples.

“…Hardware implementation in application-specific integrated circuit (ASIC) devices will require not only cryptographic algorithms but also algorithms for lightweight cryptography [1]. And in hardware implementations, the important measurements for evaluating lightweight properties are chip size and power consumption [2,3].…”

Section: Introductionmentioning

confidence: 99%

Trivium hardware implementations for power reduction

Mora

Jimenez-Fernandez

Barrero

2016

This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non-linear feedback shift registers. In 2008, it was chosen as a finalist for the hardware profile of the eSTREAM project. So that their power consumption values can be compared and verified, the proposed low-power Trivium designs were implemented and characterized in 350-nm standard-cell technology with both transistors and gate-level models, in order to permit both electrical and logical simulations. The results show that the two designs decreased average power consumption by between 15% and 25% with virtually no performance loss and only a slight overhead (about 5%) in area.