UBERNoC

Farrokhbakht, Hossein; Kao, Henry; Jerger, Natalie Enright

doi:10.1145/3313231.3352362

Cited by 12 publications

(3 citation statements)

References 10 publications

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“…For input units that are common in most of the router designs, studies targeting at lower power consumption and higher energy efficiency can generally be categorized into two groups. Firstly, shared buffer design was proposed to utilize the imbalance of different VCs in the input unit to save both power and area [19]. Secondly, there were also works focusing on implementing energy-/area-efficient input units with other memory devices and a typical example was STT-MRAM.…”

Section: Related Workmentioning

confidence: 99%

“…There are works focusing on cutting the power of routers with power gating [5]- [8] or dynamic voltage and frequency scaling [9], proportionally supplying power to the network based on the actual demand [10], completely eliminating routers (hence also buffers) through smart wiring [11] or improving the energy efficiency of networks through prediction [12], multicasting [13], traffic compression [14], pipeline bypassing [15] and hybrid flow control mechanisms [16]- [18]. When looking at the input units particularly, there are existing works having shared buffer design [19] or focusing on implementing energy-/area-efficient input units with other memory devices than the baseline static random-access memory (SRAM), such as planar embedded DRAM (eDRAM) [20] or spintronic domain-wall memory (DWM) [21]. Moreover, STT-MRAM (short for Spin Transfer Torque Magnetoresistive Random Access Memory) has also been used in NoC routers [22], [23].…”

Section: Introductionmentioning

confidence: 99%

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Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks

LIU

GAO

et al. 2023

IEICE Trans. Electron.

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The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks

LIU

GAO

et al. 2023

IEICE Trans. Electron.

View full text Add to dashboard Cite

show abstract

“…Simplified microarchitectures achieve power and area savings by simplifying and eliminating certain router structures. Existing research mainly focuses on buffers [15][16][17], as buffers contribute a relatively large portion of the area and power consumption of NoC. However, the reduction in the number and depth of buffers also greatly limits the network throughput.…”

Section: Introductionmentioning

confidence: 99%

UBMR:A low-power and low-area multicastrouter with unified buffers forNetwork-on-Chips

Ouyang,

wang,

et al. 2024

Preprint

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Network-on-Chip(NoC) has become a promising communicationparadigm for Multi-Processors System-on-Chip (MPSoC) due to its highcommunication efficiency, good scalability, and high reliability. In prac-tice, in addition to one-to-one unicast traffic in NoC, there is also a largeamount of one-to-many multicast traffic. The traditional unicast-basedmechanism for handling multicast traffic leads to a large number of repet-itive and redundant packets in the network, which rapidly consumes thenetwork bandwidth and dramatically reduces the performance of the net-work. Meanwhile, with the continuous scaling of the chip fabrication pro-cess, the power consumption increases dramatically, which also makes theNoC design face great challenges. To mitigate these problem, we proposea tree-based multicast routing algorithm to ensure that multicast pack-ets and their copies reach the destination router all through the shortestpath. For better compatibility with our proposed routing algorithm, wealso propose a unified buffer multicast router architecture, which not onlysimplifies the multicast routing algorithm, but also reduces the powerconsumption and the area overhead of the router. Detailed simulationresults show that the number of packets transmitted in the networkis reduced by 28%, and the area and power consumption are reducedby 40.6% and 38.6%, respectively, compared to conventional routers.

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An efficient NoC router by optimal management of buffer read and write mechanism

Fard

Jamali

Màsdàrí

et al. 2022

Microprocessors and Microsystems

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UBERNoC

Cited by 12 publications

References 10 publications

Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks

Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks

UBMR:A low-power and low-area multicastrouter with unified buffers forNetwork-on-Chips

An efficient NoC router by optimal management of buffer read and write mechanism

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