UHiFET - A new high-frequency High-Voltage device

Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well Process

“…5). Even if the structure can survive the breakdown stress, the existence of such a parasitic results in excess phase rotation along the stages which deteriorates the phase alignment between them; hence the overall output power and efficiency will decrease if not compensated properly [3] - [4], [8] - [9]. To do so, an additional mechanism needs to be deployed, which is done through a capacitance feed from the drain back to the source of each common gate stage (see Fig.…”

“…Vout = NVD1. This however is not achieved easily due to the fact that the core transistor parasitics are inevitably present, which are very well explained in [3] - [4]. However, this is not the case when it comes to bulk CMOS processes as they pose parasitics, which tend to drastically deteriorate the overall PA performance.…”

“…Not only that but also, as is explained in the following sections, this will eventually end in PA breakdown. Accordingly, [3] - [4] lack the adequate behavioral parasitic models while the proposed methods explained in [2] - [9] prove insufficient when designing bulk CMOS PAs. This paper is devoted to design stacked CMOS transistor PAs in bulk CMOS deploying the so-called triple-well/deep nwell process technique and its corresponding issues.…”

Performance Improvement of Multi-Stacked CMOS mm-Wave Power Amplifiers Based on Negative Capacitance Phase Compensation

“…2(b)). [8] Proposed a shunt capacitor tuning technique, which was fed back from drain to source (Fig. 2(c)).…”

“…To overcome the issue, stacking transistors was proposed, [1]- [4]. Due to the presence of transistor parasitics, though, stacking topology requires additional networks for inter-stage matching and phase alignment of each and every amplifier stage in order for the signals to be efficiently superimposed up to the output node [5]- [8]. In this respect, the current paper presents a novel method based on negative capacitance parasitic effect cancellation which yields reduced phase rotation along the stacks and hence inter-stage phase misalignment, which improves the overall PA performance.…”