2022
DOI: 10.1016/j.measurement.2022.111874
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Ultra compact pulse shrinking TDC on FPGA

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Cited by 7 publications
(3 citation statements)
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“…The measured resolutions at different temperatures are plotted in Fig. 10 against results from a pulse shrinking TDC [28]. An observable improvement in the temperature stability is confirmed.…”
Section: B Resolution Temperature Stabilitymentioning
confidence: 79%
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“…The measured resolutions at different temperatures are plotted in Fig. 10 against results from a pulse shrinking TDC [28]. An observable improvement in the temperature stability is confirmed.…”
Section: B Resolution Temperature Stabilitymentioning
confidence: 79%
“…3) The different driving capability and loading effect of an in-homogeneous gate results in aspect ratio variation between adjacent gates [28]; 4) The hysteresis effect on a SOI based CMOS circuit leads to delay variations [31]. Fortunately, level restorers abstracted in Fig.…”
Section: B Resolution Temperature Stabilitymentioning
confidence: 99%
“…The essence of FPGA is to design a chip. Its development process is compiled, integrated, laid out and wired by EDA tools through Verilog and other hardware description languages, and finally loaded into the FPGA device to complete the realized functions [4]. The hardware description language describes the combinatorial logic and sequential logic circuit, the degree and logic are the circuit composed of and, not, or, and the sequential circuit is the trigger.…”
Section: Basic Knowlagent Of Fpgamentioning
confidence: 99%