Ultra-Fast Downloading of Partial Bitstreams through Ethernet

Bomel, Pierre; Crenne, Jérémie; Ye, Linfeng; Diguet, Jean-Philippe; Gogniat, Guy

doi:10.1007/978-3-642-00454-4_10

Cited by 17 publications

(13 citation statements)

References 8 publications

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“…Dynamic and secure installation of data has been explored in the context of FPGAs [2], which is similar to our problem, but with different security goals (protection of IP of more concern than installation of a compromised bitfile). Also, this work assumes local area network connections to derive some security properties.…”

Section: Related Workmentioning

confidence: 97%

System-Level Security for Network Processors with Hardware Monitors

Wolf

Teixeira

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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New attacks are emerging that target the Internet infrastructure. Modern routers use programmable network processors that may be exploited by merely sending suitably crafted data packets into a network. Hardware monitors that are co-located with processor cores can detect attacks that change processor behavior with high probability. In this paper, we present a solution to the problem of secure, dynamic installation of hardware monitoring graphs on these devices. We also address the problem of how to overcome the homogeneity of a network with many identical devices, where a successful attack, albeit possible only with small probability, may have devastating effects.

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Section: Related Workmentioning

confidence: 97%

System-Level Security for Network Processors with Hardware Monitors

Wolf

Teixeira

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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“…For sure, VDSS executed on ARM cores can get extremely close to the physical devices' bandwidth limit. Previous works [10] proved that a 100Mbits Ethernet controller can be saturated by a relatively slow processor. Such a possibility, with a new Ethernet protocol, has been applied to partial reconfiguration of FPGAs.…”

Section: F About Performancesmentioning

confidence: 99%

Virtual Devices for Hot-Pluggable Processors

Bomel

Martin

Diguet

2014

2014 17th Euromicro Conference on Digital System Design

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When partially reconfigurable, FPGA-based, systems allow to dynamically hot-plug processors, the number of possible software configurations increases and the dynamic sharing of hardware peripherals becomes problematic. Moreover, the debugging of application processes, which needs physical devices to communicate with remote users or debuggers, is a critical service that becomes extremely difficult to implement. This work puts forward the concept of virtual devices to reduce software complexity and isolate system services from applications. It is illustrated by a methodology making the design of debug paths easier. Several experiments show that heterogeneous systems of up to 24 hot-pluggable processors can take advantage of virtual devices.

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“…In this work, we employ a widely used open-source communication and synchronization framework called Simple Interface for Reconfigurable Computing (SIRC) [11,25] distributed by Microsoft to facilitate the PC-FPGA intercommunication via Ethernet. A methodology to sent partial bitstreams to FPGA over an Ethernet connection has been described previously [5,6]. Compared to this work we found, an extension of the SIRC framework to be more promising for transferring the partial bitstream to the FPGA, as they provide sufficient isolation of the DPR controller from the Ethernet communication interface.…”

Section: Introductionmentioning

confidence: 94%

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet

Johnson

Saha

Chakraborty

et al. 2014

Proceedings of the 9th Workshop on Embedded Systems Security

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We describe a novel methodology to exploit the widely used Dynamic Partial Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryption circuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file over an Ethernet connection to the FPGA board, from an attacker's computer which can communicate with the FPGA over a network. The inserted Trojan launches a "fault attack" on the AES encryption circuit, which enables recovery of the secret key by standard mathematical analysis of the faulty ciphertext produced. To the best of our knowledge, this is the first reported attack which exploits DPR to break an AES hardware implementation on FPGA. Our implementation results establish this to be an extremely potent attack on AES at low hardware and computational overhead, while using the standard unlicensed FPGA design tools.

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Ultra-Fast Downloading of Partial Bitstreams through Ethernet

Cited by 17 publications

References 8 publications

System-Level Security for Network Processors with Hardware Monitors

System-Level Security for Network Processors with Hardware Monitors

Virtual Devices for Hot-Pluggable Processors

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet

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