Ultra-high-speed and universal-coding-rate Viterbi decoder VLSIC-SNUFEC VLSI

Abstract

An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSlC with coding rates from onehalf to fifteen-sixteenth and a constraint length of seven for fotward error correction (FEC) has been developed using 0.8-pm semi-custom CMOS LSlC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-statetransition (SST) Viterbi decoding scheme and lowpower-consumption burst-mode-selection (BMS) path mempry have been employed. In addition, a new maxirhum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSlC achieves a maximum data rate of 6OMbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.

Low-power CMOS and BiCMOS circuits for analog convolutional decoders

“…Fig. 2(a) shows the trellis module for the case where two transitions enter and leave each state (the case most frequently encountered in practice [2]). The calculations required in each state of the trellis module shown in Fig.…”

“…Such a deviation would cause negligible loss of coding gain [10]. The main parameters of circuits 1 and 2 are summarized in Table I, together with those of [6] and a typical digital unit [2] for comparison purposes.…”

“…We present two circuits, one in BiCMOS and the other in CMOS technology. The BiCMOS circuit is especially suitable for use in digital magnetic recording applications (where this technology is used in other parts of the system [7]), while the CMOS realization is more suitable for convolutional decoders which are typically realized in digital CMOS technology [2].…”

“…Practical applications of MLSD include decoders for convolutional codes [2] and detectors for partial-response signaling (PRS) in digital magnetic recording systems [3]. Although practical Viterbi decoders generally employ digital signal processing (DSP), e.g., digital mobile radio or digital hardware (e.g., digital satellite TV), analog circuits have been employed recently to realize certain sections of these decoders, notably the branch metric computer (BMC) and add-compare-select (ACS) blocks, as shown in Fig.…”

Very Low Power Viterbi Decoder Employing Minimum Transition and Exchangeless Algorithms for Multimedia Mobile Communication

“…Because the scheme shows powerful forward error correction performance and the great progress in CMOS technology makes it possible to realize the high speed, low power encoders/decoders [4]. A viterbi decoder [5,6] is an important target for power reduction in many low power communication devices such as cellular phones, where it consumes almost one third power [7].…”