An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSlC with coding rates from onehalf to fifteen-sixteenth and a constraint length of seven for fotward error correction (FEC) has been developed using 0.8-pm semi-custom CMOS LSlC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-statetransition (SST) Viterbi decoding scheme and lowpower-consumption burst-mode-selection (BMS) path mempry have been employed. In addition, a new maxirhum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSlC achieves a maximum data rate of 6OMbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.

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A b s t r a c t This paper proposes a semi-autonomous frame synchroniz.ation scheme for a TDMA (Time Division Multiple Access) .. TDD (Time Division Duplexing) personal communication system to realize accurate frame synchronization i n a simple manner. The proposed scheme selects specific adjacent base stations by the station indicator (SID), carries out high resolution frame phase control, and compensat'es propagation delay between base stations by using geographical data. This autonomously synchronizes all base stations to each other. Computer simulation results confirm the accurate and stable TDMA frame synchronimtion of all base stations under the fading environments.

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This article presents a lecture given by Dr.