An Ultra-high-speed (higher than 60Mbps) Viterbi decoder VLSlC with coding rates from onehalf to fifteen-sixteenth and a constraint length of seven for fotward error correction (FEC) has been developed using 0.8-pm semi-custom CMOS LSlC technology. To reduce the power consumption of the one-chip high-coding-rate Viterbi decoder, a newly developed universal-coding-rate scarce-statetransition (SST) Viterbi decoding scheme and lowpower-consumption burst-mode-selection (BMS) path mempry have been employed. In addition, a new maxirhum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed to reduce the path memory length without coding-gain degradation. The developed Viterbi decoder VLSlC achieves a maximum data rate of 6OMbps with a power consumption of 2.5W and achieves near theoretical net coding-gain performance for various coding rates.

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AbstradThis paper proposes a universal-coding-rate scarce-state-transition (UCR-SST) Viterbi decoder that permits the realization of a highspeed and high-coding-rate one-chip forward error correction (FEC) CMOS LSIC. To reduce the power consumption of high-coding-rate Viterbi decoders, the proposed decoder expands the scarce-state-transition (SST) Viterbi decoding scheme from coding rate one-half to any higher coding rate. In order to employ the SST Viterbi decoding scheme for high-coding-rate convolutional codes, a universal pre-decoding scheme for convolutional codes is newly developed. Computer simulations show a drastic reduction in CMOS gate ON-OFF switching (60% reduction at Pe=lxlO-4, R=7/8). Moreover, low power consumption path memory is proposed to reduce the power consumption all over Pe. A pilot chip (1.OpmCMOS LSIC) is fabricated and its total power consumption is reduced by 27% for rate three-fourths coding rate Viterbi decoding.The excellent characteristics of the proposed scheme has opened the way to the LSIC realization of one chip high-speed and highcoding-rate Viterbi decoders.