Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping

Lallement, F.; Duriez, B.; Grouillet, A.; Arnaud, F.; Tavel, B.; Wacquant, F.; Stolk, P. A.; Woo, M.; Erokhin, Yu. N.; Scheuer, J.T.; Godet, Ludovic; Weeman, J.; Distaso, D.; Lenoble, D.

doi:10.1109/vlsit.2004.1345465

Cited by 13 publications

(11 citation statements)

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“…The die size is 2.5 mm × 2.5 mm × 0.5 mm. The junction depth is set to 20nm for the 65nm technology [Lallement et al 2004], and the Debye length is 2nm [Bienacel et al 2004]. The floorplan of a test chip having 1.2 million functional gates is shown in Figure 11(a), and the geometries of chip and package are shown in Figure 11(b).…”

Section: Resultsmentioning

confidence: 99%

“…The secondary heat flow path contains interconnect layers, I/O pads, and the print circuit board. Functional blocks of the die are modeled as many power-generating sources attached to a thin layer close to the top surface of the die with the thickness being equal to the junction depth of device [Lallement et al 2004]. Due to variations of physical parameters, the power consumption of functional blocks is treated statistically.…”

Section: Problem Formulationmentioning

confidence: 99%

“…p(r, L, t ox , T ) is the power density profile that consists of the deterministic dynamic power density profile p d (r), the statistical gate tunneling leakage power density profile p g (r, L, t ox , T ), and the statistical subthreshold leakage power density profile p s (r, L, t ox , T ). Since the major part of device current flows through the channel, power density distribution has its value only when r ∈ [Lallement et al 2004]. Generally, the values of κ(r, T ) are temperature dependent.…”

Section: Problem Formulationmentioning

confidence: 99%

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An efficient method for analyzing on-chip thermal reliability considering process variations

Lee

Huang

2013

ACM Trans. Des. Autom. Electron. Syst.

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This work provides an efficient statistical electrothermal simulator for analyzing on-chip thermal reliability under process variations. Using the collocation-based statistical modeling technique, first, the statistical interpolation polynomial for on-chip temperature distribution can be obtained by performing deterministic electrothermal simulation very few times and by utilizing polynomial interpolation. After that, the proposed simulator not only provides the mean and standard deviation profiles of on-chip temperature distribution, but also innovates the concept of thermal yield profile to statistically characterize the on-chip temperature distribution more precisely, and builds an efficient technique for estimating this figure of merit. Moreover, a mixed-mesh strategy is presented to further enhance the efficiency of the developed statistical electrothermal simulator.Experimental results demonstrate that (1) the developed statistical electrothermal simulator can obtain accurate approximations with orders of magnitude speedup over the Monte Carlo method; (2) comparing with a well-known cumulative distribution function estimation method, APEX [Li et al. 2004], the developed statistical electrothermal simulator can achieve 215× speedup with better accuracy; (3) the developed mixedmesh strategy can achieve an order of magnitude faster over our baseline algorithm and still maintain an acceptable accuracy level.

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Section: Resultsmentioning

confidence: 99%

Section: Problem Formulationmentioning

confidence: 99%

Section: Problem Formulationmentioning

confidence: 99%

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An efficient method for analyzing on-chip thermal reliability considering process variations

Lee

Huang

2013

ACM Trans. Des. Autom. Electron. Syst.

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“…The thickness of the power source layer is set to be 20 nm which is the nominal value of the device junction depth for the 65-nm technology [26]. The equivalent heat transfer coefficient of the primary heat flow path, , is 8700 W m C [6], and the equivalent heat transfer coefficient of the secondary heat flow path, , is 2017 W m C .…”

Section: A Accuracy and Fast Convergence Of The Git-based Thermal Simentioning

confidence: 99%

Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms

Huang

Lee

2009

IEEE Trans. VLSI Syst.

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The capability of predicting the temperature profile is critically important for timing estimation, leakage reduction, power estimation, hotspot avoidance and reliability concerns during modern IC design. This paper presents an accurate and fast analytical full-chip thermal simulator for early-stage temperature-aware chip design. By using the generalized integral transforms (GIT), an accurate formulation is derived to estimate the temperature distribution of full-chip with a truncated set of spatial bases which only needs very small truncation points. Then, we develop a fast Fourier transform like evaluating algorithm to efficiently evaluate the derived formulation. Experimental results confirm that the proposed GIT-based analyzer can achieve an order of magnitude speedup compared with a highly efficient Green's function-based thermal simulator. Finally, we propose a 3-D IC thermal simulator and demonstrate its efficiency and accuracy.

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“…We developed a novel method of PD combined with helium plasma pre-amorphization (He-PA) process which has the advantage of high optical absorption property during annealing and achieved a great advantage over the LEII on junction performance in terms of sheet resistance and junction abruptness by using fast speed annealing methods such as laser annealing and FLA [1][2][3]. PD process was also successfully integrated into the conventional 65nm CMOS transistor fabrication flow and showed higher drive current compared to LEII [4].…”

Section: Introductionmentioning

confidence: 99%

Hard X-ray Photoelectron spectroscopy (HX-PES) study on chemical binding states of ultra shallow plasma-doped silicon layer for the application of advanced ULSI devices

Jin¹,

Sasaki²,

Okashita³

et al. 2006

2006 International Workshop on Junction Technology

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We took HX-PES measurement (Si Is) on silicon samples doped by plasma doping (PD) for the first time before and after annealing using either spike RTA or flash lamp anneal (FLA) in SPring-8. After PD, the carrier density of n-Si substrate decreased to intrinsic Si level due to defect induced carrier traps. After annealing, the results revealed that the chemical binding states of the doped samples were well recovered showing high impurity activation.

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Ultra-low cost and high performance 65nm CMOS device fabricated with plasma doping

Cited by 13 publications

References 0 publications

An efficient method for analyzing on-chip thermal reliability considering process variations

An efficient method for analyzing on-chip thermal reliability considering process variations

Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms

Hard X-ray Photoelectron spectroscopy (HX-PES) study on chemical binding states of ultra shallow plasma-doped silicon layer for the application of advanced ULSI devices

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