No abstract

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trapassisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V DS = −0.5 V, good short-channel effect control, and high transconductance (g m = 1.2 mS/µm at V DS = −1 V and 1.05 mS/µm at V DS = −0.5 V for L G = 70 nm). The Ge FinFET presented in this paper exhibits the highest g m /SS sat at V DD = 1 V reported for nonplanar unstrained Ge p-FETs to date.Index Terms-Aspect ratio trapping (ART), band-to-band tunneling (BTBT), epitaxy, FinFET, germanium, scaling, trap-assisted tunneling (TAT).

No abstract

V t -mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control.We show by simulations and by measurements that in FinFETs, unlike planar bulk, β-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in β-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

We report the first demonstration of scaled Ge p-channel FinFET devices fabricated on a Si bulk FinFET baseline using the Aspect-Ratio-Trapping (ART) technique [1]. Excellent subthreshold characteristics (long-channel subthreshold swing SS=76mV/dec at 0.5V), good SCE control and high transconductance (1.2 mS/µm at 1V, 1.05 mS/µm at 0.5V) are achieved. The Ge FinFET presented in this work exhibits highest g m /SS at V dd =1V reported for non-planar unstrained Ge pFETs to date.