Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

Ni, Chi-Nung; Rao, K. V.; Khaja, Fareen Adeni; Sharma, Shashank; Tang, Shan; Chen, J. J.; Hollar, K.; Breil, N.; Li, X.; Jin, Miao; Lazik, C.; Lee, J.; Maynard, Helen; Variam, N.; Mayur, A. J.; Kim, S.; Chung, Hua; Chudzik, M.; Hung, R.; Yoshida, N.; Kim, N.

doi:10.1109/vlsit.2016.7573383

Cited by 31 publications

(18 citation statements)

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“…Therefore, to reduce the resistivity, increasing the active carrier concentration in the semiconductor side is supposed to be a strategy of choice. In fact, the required level of specific contact resistivity for future nodes is going to be less than 1 × 10 −9 Ω cm 2 [33,34]. To achieve such a low resistivity of the contact, the active carrier concentration needs to be close to 1 × 10 21 at./cm 3 [35,36], or even higher [37].…”

Section: Mol Applicationsmentioning

confidence: 99%

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

et al. 2022

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The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.

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Section: Mol Applicationsmentioning

confidence: 99%

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

et al. 2022

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“…owadays, the area of transistors is so small that metalsemiconductor contact resistivity dominates parasitic components of access resistance [1]. The improvement of the contact resistivity has therefore become more and more challenging in recent years and a target for future nodes is to achieve a value below 1×10 -9 ohm.cm 2 [2]. The required breakthrough is demonstrated for p-type contact by using gallium (Ga) as the dopant in high germanium (Ge) content silicon-germanium (SiGe) alloys [3], [4] and pure Ge [4], where a key phenomenon is dopant surface segregation during non-equillibrium solidification induced by nanosecond melt laser annealing (MLA).…”

Section: Introductionmentioning

confidence: 99%

3D Simulation for Melt Laser Anneal Integration in FinFET’s Contact

Tabata

Curvers

Huet

et al. 2020

IEEE J. Electron Devices Soc.

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“…8,24 In parallel, some reports can be found on a trial of integrating laser anneal into industrial transistors, especially to reduce the contact resistivity. 23,[25][26][27][28][29] In a real CMOS process, multilayered structures can be found everywhere. A typical one is a semiconductor material encapsulated by a dielectric thin film as found in the gate of transistor (i.e., Si gate with silicon dioxide (SiO 2 ) hard mask).…”

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confidence: 99%

Non-Equilibrium Growth of Surface Wrinkles Emerging in an SiO₂/Si Stack during Si Melting Induced by UV Nanosecond Pulsed Laser Annealing

Karmous

Rozé

Raynal³

et al. 2022

ECS J. Solid State Sci. Technol.

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UV nanosecond pulsed laser annealing (UV-NLA) is demonstrating clear benefits in emerging 3D-integrated electronic devices, where the allowed thermal budget is strictly limited to preserve underlying device performance. A possible drawback of UV-NLA is that melting a solid substrate covered by a dielectric layer, which can be found in typical electronic device structures, induces wrinkles on the surface and may be an issue for subsequent processes. In this study, UV-NLA is performed in SiO2/Si structures to systematically investigate the emergence of wrinkles. A classical analytical model shows good agreement with our experimental results if a fitting coefficient is involved. Interestingly, its value rapidly increases for a thinner SiO2 film, whereas it becomes closer to unity for a thicker SiO2 film. This might infer a possible discrepancy of the material properties taken from literature and those of real industrial thin SiO2 films. The degree of the initial SiO2 film stress being negligible compared to the SiO2 shear modulus, its impact on the growth of wrinkles is not significant in our experiment.

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Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

Cited by 31 publications

References 1 publication

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

3D Simulation for Melt Laser Anneal Integration in FinFET’s Contact

Non-Equilibrium Growth of Surface Wrinkles Emerging in an SiO₂/Si Stack during Si Melting Induced by UV Nanosecond Pulsed Laser Annealing

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Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

Cited by 31 publications

References 1 publication

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

3D Simulation for Melt Laser Anneal Integration in FinFET’s Contact

Non-Equilibrium Growth of Surface Wrinkles Emerging in an SiO2/Si Stack during Si Melting Induced by UV Nanosecond Pulsed Laser Annealing

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Product

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Non-Equilibrium Growth of Surface Wrinkles Emerging in an SiO₂/Si Stack during Si Melting Induced by UV Nanosecond Pulsed Laser Annealing