Advanced material properties and sophisticated layer structures of SiGe hetero field-effect transistors are the basis for expected [ I ] and partly demonstrated elevated RF and noise performance of these devices [2]. However, a lack of lateral device optimization, due to lithography restrains and non self-aligned technology processes often limits the electrical performance of these transistors.Self-aligned technology concepts for hetero field-effect transistors often fail because of the incompatibility between metal gates and high temperature process steps. The new fully optical, selfaligned integration concept presented here uses a replacement-gate structure to overcome this problem ( Fig. 1). In contrast to conventional SiGe HFET technologies, which apply e-beam lithography the dummy-gate structure is defined optically. Polyimide is utilized as the favored dummygate material, because it is easy to handle by spin on, has a high temperature stability and is removable without damages from the heterostructure. The replacement gate acts as a mask for the selfaligned sourceidrain implantation and the low ohmic Ni salicidation of the contacts. The final physical gate length is achieved by a dry etching plasma step, which shrinks the polyimide to sub 100 nm dimensions (Fig. 2). Then Si02 passivation takes place and a planarization process ensures a flat device topography. With an isotropic etch-back step the replacement-gate is revealed again for wet chemical removal. After rapid thermal annealing at 600 "C for 30 s, Pt/Ti evaporation forms a Schottky-contact at the bottom of the gate trench. The following Au electroplating process is the best choice to fill the high aspect ratio gate trench and to deposit a thick homogenous metallization layer. In a final etching step the metallization layer is patterned and the size of the gate head is defined independently from the gate-length L , . The flexibility of this technology concept allows also the realization of a MOS-or pn-junction HFET with only slight changes in the process flow and it is even applicable for IIW HEMTs. Fig. 3 shows the transfer characteristic of a 90 nm gate-length device. An outstanding result is the high extrinsic transconductance g, with a maximum value of 685 mWmm (gmi = 882 mS/mm) at a gate bias of 0.2 V. Furthermore the transistor exhibits an elevated Ion/I0f ratio of 5 1 .2*103 and an excellent pinch-off behavior. Considering the ID(VDs)-curves we find a large saturation current beyond 500 mA/mm at VDS = 1.5 V and VG = 0.7 V (Fig. 4) and a high breakdown voltage of about 4.0 V S-parameters were measured on-wafer in the range from 2 to 50 GHz. The deembedded highest fT was found to be 90 GHz for the 90 nm device (Fig. 5). Compared to the best results of the conventional technology an enhancement of around 20 % was achieved (Fig. 6). The obtained g, and fs results are the highest values reported so far for SiGe n-HFET [3], [4]. Distinctly higher frequencies are expected for a SiGe MOS version, which allows L,, towards zero.
