Ultra thinning 300-mm wafer down to 7-&amp;#x00B5;m for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

Kim, Y. S.; Tsukune, A.; Maeda, Noritoshi; Kitada, Hideki; Kawai, Akihito; Arai, K.; Fujimoto, Koji; Suzuki, Kenkichi; Mizushima, Y.; Nakamura, Tomoji; Ohba, Takayuki; Futatsugi, T.; Miyajima, M.

doi:10.1109/iedm.2009.5424349

Cited by 22 publications

(15 citation statements)

References 2 publications

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“…UTCs with thicknesses <20 lm have been explored by many groups to obtain a compact high-performance flexible electronics by using techniques such as post-process wafer thinning by grinding or chemical etching 30,40 (e.g., Circonflex process 41 ) and porous Si (e.g., Chipfilm TM technology 42 ). The strength of UTCs varies with the methods adopted to obtain them.…”

Section: Ultra-thin Chips and Mechanical Bendingmentioning

confidence: 99%

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Heidari

Wacker

Dahiya

2017

Applied Physics Reviews

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Electronics that conform to 3D surfaces are attracting wider attention from both academia and industry. The research in the field has, thus far, focused primarily on showcasing the efficacy of various materials and fabrication methods for electronic/sensing devices on flexible substrates. As the device response changes are bound to change with stresses induced by bending, the next step will be to develop the capacity to predict the response of flexible systems under various bending conditions. This paper comprehensively reviews the effects of bending on the response of devices on ultra-thin chips in terms of variations in electrical parameters such as mobility, threshold voltage, and device performance (static and dynamic). The discussion also includes variations in the device response due to crystal orientation, applied mechanics, band structure, and fabrication processes. Further, strategies for compensating or minimizing these bending-induced variations have been presented. Following the in-depth analysis, this paper proposes new mathematical relations to simulate and predict the device response under various bending conditions. These mathematical relations have also been used to develop new compact models that have been verified by comparing simulation results with the experimental values reported in the recent literature. These advances will enable next generation computer-aided-design tools to meet the future design needs in flexible electronics.

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Section: Ultra-thin Chips and Mechanical Bendingmentioning

confidence: 99%

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Heidari

Wacker

Dahiya

2017

Applied Physics Reviews

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“…The successful implementation of 3D architectures can happen only through a thorough and comprehensive characterization of the stress inside and around TSVs. So far, studies have focused primarily on the fabrication and electrical characterization of TSVs [7][8][9]. In addition to these aspects of TSVs, an equally important but less discussed area is the stress and quality characterization of the TSV interface.…”

Section: Introductionmentioning

confidence: 99%

Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA

Lee¹,

Kim²,

Jeon³

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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As Moore predicted in 1965, the scale of microelectronic devices continues to diminish at tremendous speed, and today the limitations of conventional 2D scaling make such 3D applications as TSV (through-silicon via) and high-stacked thin-die packaging technologies extremely attractive. However, their complicated structures and thermal-cycled processes generate enormous interfacial stresses. In particular, TSV-to-CPB (copper pillar bump)-stacked structures manufactured under various processing conditions have serious stress-induced reliability problems: stresses can be high enough to cause delaminated or open-crack failures. Many technologies have been developed for measuring residual stress, but destructive techniques such as the holedrilling and cutting methods are too bulky to use at microscales and non-destructive techniques such as XRD (Xray diffraction), BN (Barkhausen noise) and the curvature method using the Stoney equation yield averaged results that are inappropriate in the local assessment of TSV and CPB interfaces. NIT (nanoinstrumented indentation testing), on the other hand, offers many advantages since it can give a micropartial characterization of stress using the load difference between samples with different residual stresses at the same depth. Here we introduce an algorithm to measure the micropartial residual stress between CPB and TSV through nanoinstrumented indentation testing. To verify our measured outputs, we observe cross-sectioned microstructure of TSV and CPB using an ion miller and ion-beam image by FIB (focused ion beam), and discuss the textures of variously structured and processed TSV and CPB interfaces. In addition, we used finite element analysis (ABSYS) to simulate the stress distribution around them. Our study will, we hope, be useful in reliability-based quantitative design by defining keep-out zones between TSVs.Keywords: TSV (through silicon via); Micropartial residual stress; NIT (nanoinstrumented indentation testing); Grain growth model; 3DI (3-dimensional integration). IntroductionAs conventional 2D scaling of microelectronic devices has severe limitations, 3D chip stacking is clearly attractive for high performance at low cost in applications such as CMOS image sensors (CIS), stacked memories, highperformance processor-memory assemblies and advanced system-in-package (SiP) leading to heterogeneous integration.

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“…So far, studies mainly focus on the fabrication and electrical characterization of TSVs [6][7][8]. In addition to those understandings of TSVs, an equally important but less discussed area is the quality of the TSV interface.…”

Section: Introductionmentioning

confidence: 99%

Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

Yang

Labie

Ling

et al. 2010

Microelectronics Reliability

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Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

Cited by 22 publications

References 2 publications

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA

Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

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