Ultralow-Energy Variation-Aware Design: Adder Architecture Study

Dorosti, Hamed; Teymouri, Ali; Fakhraie, S.M.; Salehi, Mostafa E.

doi:10.1109/tvlsi.2015.2426113

Cited by 6 publications

(2 citation statements)

References 15 publications

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“…Simpler computational building blocks consume lower energy and observe lower performance variations too. Finally, we conclude that utilizing such blocks in a massively parallel architecture is another way to compensate the process variation effects and lower the frequency uncertainty plus lowering timing fluctuations due to process variations [5].…”

Section: Pipe Lining and Parallel Processing For Low Powermentioning

confidence: 88%

Research on High Speed Low Power Digital Logic Family for Pipelined Arithmatic Logic Structures

2019

IJITEE

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The bit size of the data length process depends on the clock speed operation .the clock speed increases with the bit size of the data length .but this increases deal in the circuit to overcome this pipeline and parallel processing is used. This will increase the performance of the circuit with the advancement of the high speed technology the data length process per clock is increasing rapidly from Intel 1 intel20 to Intel series. Adder is an important adder structure design which uses parallel and pipelining scheme are RCA and SFA. To design these adders we need high speed processing digital electronic circuit which must be high speed and low power. There are various types of logic families which we are discuss in this paper. From static to dynamic circuit design why dynamic is faster than static. and various types of dynamic circuit design structure this paper basically focus on constant delay logic style and why it is superior to other dynamic structures such as domino logic ,dynamic logic np CMOS logic,C2MOS logic ,NORA CMOS logic design, Zipper CMOS,FTL logic.

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Section: Pipe Lining and Parallel Processing For Low Powermentioning

confidence: 88%

Research on High Speed Low Power Digital Logic Family for Pipelined Arithmatic Logic Structures

2019

IJITEE

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“…The adder circuitry, as a frequently used arithmetic unit in many ultra-low-power applications [10,11], also suffers from these problems in the subthreshold region. Numerous studies have been conducted on subthreshold adder design.…”

Section: Introductionmentioning

confidence: 99%

A Subthreshold Bootstrapped SAPTL-Based Adder Design

Zhang

Chen

2019

Electronics

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This paper proposes a 16 bit subthreshold adder design using bootstrapped sense amplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance degradation and enhance the immunity to process variations in the subthreshold region. Through employing a bootstrapped sense amplifier including a voltage boosting part and adopting an adder architecture based on bootstrapped SAPTL, significant improvements in performance and energy efficiency can be achieved. A case study of 16 bit adders in SMIC 130 nm technology demonstrated that the proposed adder outperformed other works in terms of performance, energy consumption, and energy efficiency. Furthermore, the statistical results of the Monte Carlo analysis proved the proposed adder’s significant enhancement of robustness against process and temperature variations. At 0.3 V (TT corner, 25 °C), the proposed 16 bit adder achieved improvements of 72% in performance and 8% in energy savings, as well as a 74% reduction in energy-delay production as compared with the current design.

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