Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

Ong, Xuefen; Ho, Soon Wee; Ong, Yue Ying; Wai, Leong Ching; Kripesh, V.; Lim, Y.C.; Yeo, David; Chan, Kai Chong; Tan, Juan Boon; Sohn, Dong Kyun; Hsia, Liang Choo; Chen, Zhong

doi:10.1016/j.microrel.2008.11.015

Cited by 18 publications

(5 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As Cu/low-k interconnects started to replace traditional aluminum/silicon dioxide (Al/SiO 2 ) component in chip interconnection because of its better capacitance, device speed and signal integrity of the interconnect, such underfill criteria becomes more complex as the package reliability is affected by this low-k material, and hence, its property should also be taken into account in selection of appropriate underfill material [11][12][13]. The optimum mechanical properties of underfill such as Young's modulus, T g and CTE must be carefully determined and selected such that both solder joints and low-k interconnects can be protected from failure.…”

Section: Resultsmentioning

confidence: 99%

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Kwak

2014

J Mech Sci Technol

View full text Add to dashboard Cite

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermomechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captured deformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young's modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

show abstract

Section: Resultsmentioning

confidence: 99%

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Kwak

2014

J Mech Sci Technol

View full text Add to dashboard Cite

show abstract

“…Full capillary flow underfills (FCFUs) have been used for years to protect against the coefficient of thermal expansion (CTE) mismatch in flip chip ball grid array (BGA) packages and the effects of temperature cycling. [1][2][3][4][5][6][7][8] Eventually, the underfill approach extended to the printed circuit board arena. Underfill at the board level dominates markets such as cell phones, personal digital assistants, MP3 players, digital cameras, and automotive applications.…”

Section: Introductionmentioning

confidence: 99%

Thermomechanical Fatigue Performance of Lead-Free Chip Scale Package Assemblies with Fast Cure and Reworkable Capillary Flow Underfills

Shi

Tian

Ueda

2012

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

In this paper, we present the results of temperature cycling test for full and partial capillary flow underfilled lead-free chip scale packages (CSPs), the tests were carried out on the basis of JEDEC standard. Two kinds of representative fast cure and reworkable underfill materials are used in this study, and CSPs without underfills were also tested for comparison. The test results show that the two underfill materials reduce the thermomechanical fatigue performance of CSP assemblies. The underfill with high T g and storage modulus yielded better performance; indeed, the coefficient of thermal expansion (CTE) is also very critical to the thermomechanical fatigue performance, but its effects is not so obvious in this study owing to the similar CTEs of the underfills used. In addition, the negative effect of a partial underfill pattern is smaller than that of a full underfill pattern. Failure analysis shows that the dominant failure mode observed is solder cracking near the package and/or printed circuit board pads.

show abstract

“…In addition to solder joint integrity under temperature cycling (e.g., [1]), delamination in the low-k ILD [2][3][4][5][6][7][8], depicted in Fig. 2, under thermal processes and subsequent reliability tests also becomes a significant reliability issue.…”

Section: Introductionmentioning

confidence: 99%

“…3. This reliability issue has been properly dealt with through careful selection of the underfill [3,5,6,8]. The rule of thumb is to determine a tradeoff in the modulus and glass transition temperature (T g ) of the underfill so that both solder joints and low-k ILD are reasonably protected.…”

Section: Introductionmentioning

confidence: 99%

Structural design guideline to minimize extreme low-k delamination potential in 40nm flip-chip packages

Lai

Shih

Lee

et al. 2012

Microelectronics Reliability

View full text Add to dashboard Cite

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

Cited by 18 publications

References 9 publications

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Thermomechanical Fatigue Performance of Lead-Free Chip Scale Package Assemblies with Fast Cure and Reworkable Capillary Flow Underfills

Structural design guideline to minimize extreme low-k delamination potential in 40nm flip-chip packages

Contact Info

Product

Resources

About