Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

Flachowsky, S.; Wei, A.; Illgen, R.; Herrmann, T.; Höntschel, J.; Horstmann, Μ.; Klix, W.; Stenzel, R.

doi:10.1109/ted.2010.2046461

Cited by 65 publications

(31 citation statements)

References 43 publications

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“…1 This principle has been extensively applied to boost the performance of microelectronics devices, by introducing strain in the channel region of metal-oxide-semiconductor field-effect transistors (MOSFET). [2][3][4] Different manners of implementation have been proposed. Source and drain regions can be built of epitaxial alloys such as silicon-carbon (Si x C 1-x ) [5][6][7][8] and silicon-germanium (Si x Ge 1-x ), [9][10][11][12] that have lattice parameters different from those of the Si matrix.…”

mentioning

confidence: 99%

“…Strain and stress field maps will be presented hereafter using the symbols ε ij and σ ij with i, j = x, z being coordinates in the image plane, perpendicular to the observation axis y. With respect to the Si substrate, we define the coordinate system as x//[110],y// [1][2][3][4][5][6][7][8][9][10] and z//[001], where the z-axis corresponds to the direction normal to the surface of the substrate.…”

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confidence: 99%

“…The elastic constants defined for the cubic system of Si where x, y, and z are orthogonal {001} directions are C 11 = 165.7 GPa, C 12 = 63.9 GPa, C 44 = 79.6 GPa. In our system, the observation axis y corresponds to the [1][2][3][4][5][6][7][8][9][10] direction. Hence, to calculate the strains in the substrate, the stiffness matrix has to be rotated by 45 • around the [001] direction.…”

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confidence: 99%

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Mechanics of silicon nitride thin-film stressors on a transistor-like geometry

Reboh

Morin²,

Hÿtch

et al. 2013

APL Materials

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To understand the behavior of silicon nitride capping etch stopping layer stressors in nanoscale microelectronics devices, a simplified structure mimicking typical transistor geometries was studied. Elastic strains in the silicon substrate were mapped using dark-field electron holography. The results were interpreted with the aid of finite element method modeling. We show, in a counterintuitive sense, that the stresses developed by the film in the vertical sections around the transistor gate can reach much higher values than the full sheet reference. This is an important insight for advanced technology nodes where the vertical contribution of such liners is predominant over the horizontal part

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Mechanics of silicon nitride thin-film stressors on a transistor-like geometry

Reboh

Morin²,

Hÿtch

et al. 2013

APL Materials

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“…have not been considered, and the problem with calculating the transistor-to-transistor intrachannel stress variation and consequent variation in transistor electrical characteristics has not been addressed yet. 6 In order to be able to consider these effects, the stress simulation methodology should be capable to resolve scales of the order of a transistor size (approximately nanometers) and, to account for all major internal (layout-induced) and external (e.g., packaging) stress sources affecting a particular device. Compact modelbased approaches for the layout-induced stress effects, which typically employ the empirical modeling, 7,8 cannot take into account the package-induced variations in transistor characteristics.…”

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confidence: 99%

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Kteyan¹,

Gevorgyan²,

Hovsepyan³

et al. 2014

J. Micro/Nanolith. MEMS MOEMS

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Abstract. Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing a design of 3-D IC stacks and detecting acrossdie out-of-spec variations in MOSFET electrical characteristics caused by the die thinning and stacking-induced mechanical stress is addressed. The development of a multiscale simulation methodology for managing mechanical stresses during a sequence of designs of 3-D IC dies, stacks, and packages is focused. A set of physics-based compact models for a multiscale simulation is proposed to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 2.5D interposer-based, and true 3-D through silicon via-based technology. A simulation flow is developed for the hot-spot checking in different types of devices/circuits such as digital, analog, analog matching, memory, IO, characterized by different sensitivities to the stress-induced mobility variations. A calibration technique based on fitting to measured electrical characteristics of the test-chip devices is presented. The limited characterization or measurement capabilities for 3-D IC stacks and a strict "good die" requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield. © The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

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“…Contemporary nanotechnological applications such as light emitting diodes 1,2 or field-effect transistors [3][4][5][6] (FET) for electronic switching or non-volatile data storage rely on the detailed understanding of electronic and structural properties at the scale of a lattice constant and below. In this respect, scanning transmission electron microscopy (STEM) has become a prominent tool for the characterization of composition, 7 electric field, 8 and strain [9][10][11][12] due to its high spatial resolution between 50 pm and a few nanometres, depending on the mode of operation.…”

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confidence: 99%

Two-dimensional strain mapping in semiconductors by nano-beam electron diffraction employing a delay-line detector

Müller‐Caspary

Oelsner²,

Potapov

2015

Applied Physics Letters

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A delay-line detector is established for electron detection in the field of scanning transmission electron microscopy (STEM) and applied to two-dimensional strain mapping in Si-based field effect transistors. We initially outline the functional principle of position-sensitive delay-line detection, based on highly accurate time measurements for electronic pulses travelling in meandering wires. In particular, the detector is a single-counting device essentially providing an infinite time stream of position-resolved events so that acquisition speed is not hindered by detector read-outs occurring in conventional charge-coupled devices. By scanning the STEM probe over stressor- and gate regions of a field effect transistor on a 100 × 100 raster, 10 000 diffraction patterns have been acquired within 3–6.5 min, depending on the scan speed. Evaluation of the 004 and 220 reflections yields lateral and vertical strain at a spatial resolution of 1.6 nm. Dose-dependent strain precisions of 1.2−1.8×10−3 could be achieved for frame times of 40 and 20 ms, respectively. Finally, the detector is characterised as to quantum efficiency and further scopes of application are outlined.

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Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

Cited by 65 publications

References 43 publications

Mechanics of silicon nitride thin-film stressors on a transistor-like geometry

Mechanics of silicon nitride thin-film stressors on a transistor-like geometry

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Two-dimensional strain mapping in semiconductors by nano-beam electron diffraction employing a delay-line detector

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