Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO&lt;inf&gt;2&lt;/inf&gt;/HfO&lt;inf&gt;2&lt;/inf&gt; pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Franco, J.; Kaczer, B.; Roussel, Ph.; Mitard, J.; Sioncke, Sonja; Witters, L.; Mertens, Hans; Groeseneken, G.

doi:10.1109/iedm.2013.6724634

Cited by 47 publications

(49 citation statements)

References 14 publications

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“…1,2,4,6,15,19,20 The benefit of the Si passivation layer above GeO x -based gate stacks is its potential to improve Bias Temperature Instability (BTI) reliability. 4,36 It is important to avoid surface segregation of Ge through the Si layer during the epitaxial growth as this leads to an increase of the interfacial trap density and distribution in the finalized gate stack. 20 On the other hand, the Si passivation layer has to be sufficiently thin to approach an Equivalent Oxide Thickness (EOT) close to 1 nm as implemented in the current 14 nm-node Fin-FET.…”

Section: In Ref 2)mentioning

confidence: 99%

Processing Technologies for Advanced Ge Devices

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Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

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Section: In Ref 2)mentioning

confidence: 99%

Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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“…It has been speculated that the degradation in GeO 2 /Ge device is caused by hole trapping at low energy levels [8]. However, detailed information of these hole traps, such as the energy distribution, the differences from those in Si devices, and their corresponding degradation kinetics, have not been discussed.…”

Section: Introductionmentioning

confidence: 99%

“…Both are deposited on top of the Ge channel. With the Si-capped device it has been reported that bias induced degradation can be lower than its Si counterpart [8]. GeO 2 /Ge devices, on the other hand, offer higher mobility for both p and n MOSFETs [9].…”

Section: Introductionmentioning

confidence: 99%

“…Germanium, due to its high intrinsic hole mobility, is considered as one of the strong candidates to replace Si in MOSFETs for future technology nodes [2][3][4][5][6][7][8][9][10][11]. Two advanced gate stack fabrication approaches have been demonstrated [3][4][5], and high hole mobility has been reported [6][7][8]. One approach is with Al 2 O 3 /GeO 2 and the other is with HfO 2 /SiO 2 /Si-cap.…”

Section: Introductionmentioning

confidence: 99%

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A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO₂/Ge and SiON/Si pMOSFETs

Zhang

et al. 2016

IEEE Trans. Electron Devices

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Abstract-High mobility germanium (Ge) channel is considered as a strong candidate for replacing the Si in pMOSFETs in near future. It has been reported that the conventional power-law degradation kinetics of Si devices is inapplicable to Ge. In this work, further investigation is carried out on defect energy distribution, which clearly shows that this is because the defects in GeO 2 /Ge and SiON/Si devices have different physical properties. Three main differences are: 1) Energy alternating defects (EAD) exist in Ge devices but insignificant in Si; 2) The distribution of as-grown hole traps (AHT) has a tail in the Ge band gap but not in Si, which plays an important role in degradation kinetics and device lifetime prediction; 3) EAD generation in Ge devices requires the injected charge carriers to overcome a 2 nd energy barrier, but not in Si. Taking the above differences into account, the power law kinetics of EAD generation can be successfully restored by following a new procedure, which can assist in the Ge process/device optimization.

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“…[5][6][7][8][9] Si-passivation is advantageous over GeO xbased gate stack in terms of Bias Temperature Instability (BTI) reliability. [10][11][12][13][14] Ge surface segregation during the epitaxial Si growth needs to be avoided as it leads to an increase of the interfacial trap density and distribution in the final gate stack. 10,15,16 On the other hand, the Si passivation layer has to be sufficiently thin.…”

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confidence: 99%

Editors' Choice—Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures

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Arimura

Cott

et al. 2018

ECS J. Solid State Sci. Technol.

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Epitaxially grown ultra-thin Si layers are often used to passivate Ge surfaces in the high-k gate module of (strained) Ge FinFET and Gate All Around devices. We use Si 4 H 10 as Si precursor as it enables epitaxial Si growth at temperatures down to 330 • C. C-V characteristics of blanket capacitors made on Ge virtual substrates point to the presence of an optimal Si thickness. In case of compressively strained Ge fin structures, the Si growth results in non-uniform and high strain levels in the strained Ge fin. These strain levels have been calculated for different shapes of the Ge fin and in function of the grown Si thickness. The high strain is the driving force for potential (unwanted) Ge surface reflow during Si deposition. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and can be avoided by carefully selected process conditions.

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Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO<inf>2</inf>/HfO<inf>2</inf> pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Cited by 47 publications

References 14 publications

Processing Technologies for Advanced Ge Devices

Processing Technologies for Advanced Ge Devices

A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO₂/Ge and SiON/Si pMOSFETs

Editors' Choice—Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures

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Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO<inf>2</inf>/HfO<inf>2</inf> pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

Cited by 47 publications

References 14 publications

Processing Technologies for Advanced Ge Devices

Processing Technologies for Advanced Ge Devices

A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO2/Ge and SiON/Si pMOSFETs

Editors' Choice—Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures

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A Comparative Study of Defect Energy Distribution and Its Impact on Degradation Kinetics in GeO₂/Ge and SiON/Si pMOSFETs