UNISM: Unified Scheduling and Mapping for General Networks on Chip

He, Ou; Dong, Sheqin; Jang, Wooyoung; Bian, Jinian; Pan, David Z.

doi:10.1109/tvlsi.2011.2159280

Cited by 56 publications

(21 citation statements)

References 23 publications

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“…He et al [12] propose a unified flow combining task scheduling and core mapping (UNISM), and model it with a mixed integer linear programming (MILP) to support both mesh and costumed topologies. Soumya et al [13] affirm that application-specific architectures are better than regular architectures in terms of power, area and performance.…”

Section: Related Workmentioning

confidence: 99%

A novel two-phase heuristic for application mapping onto mesh-based Network-on-Chip

Wang

Liu

et al. 2016

IEICE Electron. Express

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With the growing complexity of embedded VLSI products, traditional System-on-Chip (SoC) are facing severe challenges in the aspects of communicating speed and scalability. Network-on-Chip (NoC) has emerged as a viable alternative. In NoC design, application mapping is one of the most holistic researching dimensions, which maps the cores in the application to the routers in the NoC platform. Application mapping problem usually aims to reduce communication cost and power consumption of the overall system. In this paper, we focus on application mapping onto mesh network, and propose a novel two-phase heuristic algorithm. The first phase attempts to explore the potential searching spaces, while the second phase focuses on exploiting the local optima within the searching basin. To verify the effectiveness of the algorithm, this paper performs a quantitative comparisons between our proposed method and the existing mapping methods under both real application and custom generated application benchmarks.

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Section: Related Workmentioning

confidence: 99%

A novel two-phase heuristic for application mapping onto mesh-based Network-on-Chip

Wang

Liu

et al. 2016

IEICE Electron. Express

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“…Ou He et al [10] used Unified Scheduling and Mapping algorithm for the design of network on chip router. The authors developed a graph model to consider the network irregularity and estimate communication energy and latency.…”

Section: Related Workmentioning

confidence: 99%

Design of Efficient Router with Low Power and Low Latency for Network on Chip

Deivakani¹,

Shanthi²

2016

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The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

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“…As a result, the mapping of the tasks to the cores would be based on the accurate distance between the cores which is an important constraint in mapping problem. In [21] a mixed integer linear programming task scheduling and core mapping method for regular and irregular NoC architectures is proposed. The authors presented a graph model to evaluate energy dissipation and latency.…”

Section: Literature Reviewmentioning

confidence: 99%