Universal Test Interface for embedded-DRAM testing

Miyano, Satoru; Sato, K.; Numata, Kenji

doi:10.1109/54.748805

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Literature Review1

Analysis Of Equivalent Retention Time1

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2019

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Cited by 8 publications

(2 citation statements)

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“…During the last years, several approaches targeted to check the correctness of memory systems have been proposed Dreibelbis et al (1998); Huang et al (1999); Karpovsky et al (1995); Miyano et al (1999); Pundir & Sharma (2017); Yang et al (2015). Those proposals focus on creating fault models and testing algorithms to analyse different types of memory systems.…”

Section: Literature Reviewmentioning

confidence: 99%

An expert system for checking the correctness of memory systems using simulation and metamorphic testing

Cañizares

Núñez

Lara

2019

Expert Systems with Applications

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Section: Literature Reviewmentioning

confidence: 99%

An expert system for checking the correctness of memory systems using simulation and metamorphic testing

Cañizares

Núñez

Lara

2019

Expert Systems with Applications

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“…To calculate the equivalent retention time for a target temperature, we first calculate the total amount of charge leaked from the storage capacitor during the retention-time specification at the reference temperature , i.e., 85 C. Then the leakage during the equivalent retention time at the target temperature has to be equivalent to , which is expressed in (14) (14) Therefore, the equivalent retention time at the target temperature can be obtained by (15) …”

Section: Analysis Of Equivalent Retention Timementioning

confidence: 99%

Testing Methodology of Embedded DRAMs

Yang

Chang

Chao

et al. 2012

IEEE Trans. VLSI Syst.

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The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

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Overview of status and challenges of system testing on chip with embedded DRAMS

Falter

Richter

2000

Solid-State Electronics

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Universal Test Interface for embedded-DRAM testing

Cited by 8 publications

References 9 publications

An expert system for checking the correctness of memory systems using simulation and metamorphic testing

An expert system for checking the correctness of memory systems using simulation and metamorphic testing

Testing Methodology of Embedded DRAMs

Overview of status and challenges of system testing on chip with embedded DRAMS

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