UPaRC&amp;#x2014;Ultra-fast power-aware reconfiguration controller

Bonamy, Robin; Pham, Hung-Manh; Pillement, Sébastien; Chillet, Daniel

doi:10.1109/date.2012.6176705

Cited by 17 publications

(16 citation statements)

References 7 publications

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“…We point out that the frames read/write operations are the ones taking a great portion of the overall execution time of each strategy (the SysACE read/write can be performed by a dedicated controller) and that the speed of the HwIcap is a bottle neck for this method. For our system both configuration and readback can be minimized by using dedicated hardware controller such as UPaRC [24] or FaRM [25], which performs partial dynamic reconfiguration at high speed and takes into account the power consumption factor. The footprint of a checkpoint can be optimized by just saving the binary differences between the initial bitsream and the read back one.…”

Section: Resultsmentioning

confidence: 99%

An efficient BER-based reliability method for SRAM-based FPGA

Fouad

Ghaffari

Benkhelifa

et al. 2013

2013 8th IEEE Design and Test Symposium

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Section: Resultsmentioning

confidence: 99%

An efficient BER-based reliability method for SRAM-based FPGA

Fouad

Ghaffari

Benkhelifa

et al. 2013

2013 8th IEEE Design and Test Symposium

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“…While external reconfiguration controller outside the FPGA is needed for JTAG and SelectMAP, ICAP enables internal access within the FPGA, supporting self-reconfiguration approaches. Therefore, ICAP interface has been widely used together with soft-IP processor (Xilinx Micro Blaze) or hard-IP processor (IBM PowerPC), and many studies on new interface for ICAP have been performed to enhance reconfiguration speed [13,14] or reduce hardware resources required [15]. For Zynq SoC, additional interface, called Processor Configuration Access Port (PCAP), is provided to enable PS to configure PL region [16].…”

Section: Zynq Soc Platformmentioning

confidence: 99%

Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences

2016

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We implement Zynq-based self-reconfigurable system to perform real-time edge detection of 1080p video sequences. While object edge detection is a fundamental tool in computer vision, noises in the video frames negatively affect edge detection results significantly. Moreover, due to the high computational complexity of 1080p video filtering operations, hardware implementation on reconfigurable hardware fabric is necessary. Here, the proposed embedded system utilizes dynamic reconfiguration capability of Zynq SoC so that partial reconfiguration of different filter bitstreams is performed during run-time according to the detected noise density level in the incoming video frames. Pratt’s Figure of Merit (PFOM) to evaluate the accuracy of edge detection is analyzed for various noise density levels, and we demonstrate that adaptive run-time reconfiguration of the proposed filter bitstreams significantly increases the accuracy of edge detection results while efficiently providing computing power to support real-time processing of 1080p video frames. Performance results on configuration time, CPU usage, and hardware resource utilization are also compared.

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“…Using this technology, the operating system is able to schedule hardware threads [18], without resetting the rest of the system. For real-time applications, both readback and reconfiguration overheads must be minimized using a dedicated hardware reconfiguration controller, such as FaRM [19], Uparc [20] or the solution offered by Koch et al [21]. For instance, FaRM which is used in the design test detailed later allow to process configuration with a throughput of 400 MB/s.…”

Section: B Reconfiguration Servicementioning

confidence: 99%

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

Gantel

Benkhelifa

Lemonnier

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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Heterogeneous Reconfigurable Systems-on-Chip (HRSoC) contain as their name suggests, heterogeneous processing elements in a single chip. Namely, several processors, hardware accelerators as well as communication networks between all these components. In order to leverage the programming complexity of this kind of platform, applications are described with software threads, running on processors, and hardware threads, running on FPGA partitions. Combining techniques such as dynamic and partial reconfiguration and partial readback with the knowledge of the bitstream structure offer the ability to target several partitions using a unique configuration file. Such a feature permits to save critical memory resources. In this article, we propose to tackle the issue of designing fully independent partitions, and especially to avoid the routing conflicts which can occur when using the standard Xilinx FPGA design flow. To achieve the relocation process successfully, we propose a new design flow dedicated to the module relocation, using the standard tools and based on the Isolation Design Flow (IDF), a special flow provided by Xilinx for secure FPGA applications.

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UPaRC—Ultra-fast power-aware reconfiguration controller

Cited by 17 publications

References 7 publications

An efficient BER-based reliability method for SRAM-based FPGA

An efficient BER-based reliability method for SRAM-based FPGA

Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

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