Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

Ladbury, Raymond L.; Berg, Melanie D.; Wilcox, Edward P.; LaBel, Kenneth A.; Kim, H. S.; Phan, Anthony M.; Seidleck, C.M.

doi:10.1109/tns.2013.2285517

Cited by 9 publications

(3 citation statements)

References 5 publications

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“…Examples of measured quantities include: aggregate error rates, per-cell probabilities of error, and spatial/temporal error distributions. These measurements can be made using testing infrastructures ranging from industry-standard largescale testing equipment [353,354] to home-grown tools based on commodity FPGAs [16,29,55,65,90,171,263,272,[355][356][357][358] or DRAM-based computing systems [236,262,273,359,360].…”

Section: Information Flow During Testingmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Generational improvements to commodity DRAM throughout half a century have long solidified its prevalence as main memory across the computing industry. However, overcoming today's DRAM technology scaling challenges requires new solutions driven by both DRAM producers and consumers. In this paper, we observe that the separation of concerns between producers and consumers specified by industry-wide DRAM standards is becoming a liability to progress in addressing scaling-related concerns.To understand the problem, we study four key directions for overcoming DRAM scaling challenges using system-memory cooperation: (i) improving memory access latencies; (ii) reducing DRAM refresh overheads; (iii) securely defending against the RowHammer vulnerability; and (iv) addressing worsening memory errors. We find that the single most important barrier to advancement in all four cases is the consumer's lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, we recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, we propose adopting this revision in a two-step plan, starting with immediate information release through crowdsourcing and publication and culminating in widespread modifications to DRAM standards.

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Section: Information Flow During Testingmentioning

confidence: 99%

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Patel

Kim

Shahroodi

et al. 2020

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…ese measurements can be made using testing infrastructures ranging from industry-standard large-scale testing equipment [244,245] to home-grown tools based on commodity FPGAs [34,39,73,87,127,138,139,[246][247][248][249][250] or DRAM-based computing systems [74,221,[251][252][253].…”

Section: Information Flow During Testingmentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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Mass-produced commodity DRAM is the preferred choice of main memory for a broad range of computing systems due to its favorable cost-per-bit. However, today's systems have diverse system-speci c needs (e.g., performance, energy, reliability) that are di cult to address using one-size-ts-all generalpurpose DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by exploiting slack in access timings to improve performance, or implementing system-level RowHammer mitigations), we observe that designers today lack the necessary insight into commodity DRAM chips' reliability characteristics to implement these techniques in practice. In this work, we make a case for DRAM manufacturers to provide increased transparency into simple device characteristics (e.g., internal row address mapping, cell array organization) that a ect consumer-visible reliability. Doing so has negligible impact on manufacturers given that these characteristics can be reverse-engineered using known techniques; however, it has signi cant bene t for system designers, who can then make informed decisions to be er adapt commodity DRAM to meet modern systems' needs while preserving its cost advantages.To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-speci c design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM access latency; and (4) defending against RowHammer a acks. We observe that adopting solutions for any of the four goals requires system designers to make assumptions about a DRAM chip's reliability characteristics. ese assumptions discourage system designers from using such solutions in practice due to the di culty of both making and relying upon the assumption.We identify DRAM standards as the root of the problem: current standards rigidly enforce a xed operating point with no speci cations for how a system designer might explore alternative operating points. To overcome this problem, we introduce a two-step approach that reevaluates DRAM standards with a focus on transparency of reliability characteristics so that system designers are encouraged to make the most of commodity DRAM technology for both current and future DRAM chips.

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“…Some designs already exist to use FPGAs to test memory systems. The naive method for design test equipment is to use a provided evaluation board from the manufacturer, and memory slot on the board to test the memory [6], but it is constricted to the memory standard offered by the evaluation board. A more flexible design is to build FPGA-based platform for testing [7,8] that uses the serializer/deserializer (SERDES) [9] or the transceivers within FPGAs to build a test platform.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-based ATE extension module for low-cost multi-GHz memory test

Keezer

Chen

Moon

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

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This paper describes an ATE extension module that enables a low-cost test system to be applied to advanced (multi-GHz) memories. The target application is for testing memories with data rates above 3.2Gbps. The test module uses state-of-the-art FPGAs for economical autonomous pattern synthesis and comparison under the high-level supervision of a low-cost "host" test platform (ATE). The FPGA logic capabilities are complemented by custom 4-channel "pin electronics" (PE) modules with I/O performance comparable to advanced ATE. The PE modules provide input/output/bidirectional signal conditioning, including amplitude, format, timing, and preemphasis, and a "shadow sampler."

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Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

Abstract: We investigate the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and the tradeoffs involved in the use of these boards.

Cited by 9 publications

References 5 publications

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

A Case for Transparent Reliability in DRAM Systems

An FPGA-based ATE extension module for low-cost multi-GHz memory test

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