Use of electrical stress and isochronal annealing on power MOSFETs in order to characterize the effects of 60 Co irradiation

Picard, C.; Brisset, C.; Hoffmann, A.; Charles, J.‐P.; Joffre, F.; Adams, L.; Siedle, A. Holmes

doi:10.1016/s0026-2714(00)00182-7

Cited by 36 publications

(26 citation statements)

References 9 publications

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“…A complete study of the mechanisms responsible for defect creation in metal-oxide-semiconductor field-effect transistors (MOSFETs) during the high electric field stress (HEFS), (a very important stress type [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]) has been pursued. The idea is to give a complete analysis of the physicochemical processes in the gate oxide (SiO 2 ) and at the gate oxide/substrate (SiO 2 /Si) interface during HEFS, since it could not been found in the literature.…”

Section: Introductionmentioning

confidence: 99%

Physico-chemical processes in metal–oxide–semiconductor transistors with thick gate oxide during high electric field stress

Ristić

Pejović

Jakšić³

2007

Journal of Non-Crystalline Solids

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Section: Introductionmentioning

confidence: 99%

Physico-chemical processes in metal–oxide–semiconductor transistors with thick gate oxide during high electric field stress

Ristić

Pejović

Jakšić³

2007

Journal of Non-Crystalline Solids

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“…A fraction of the injected electrons creates additional electron-hole pairs in the oxide through impact ionization. [5][6][7][8] Schwalke et al used the high field stress test as an accelerated reliability testing method for the gate oxide. This is similar to the effects of ionizing radiation in MOS devices.…”

Section: Introductionmentioning

confidence: 99%

“…This is similar to the effects of ionizing radiation in MOS devices. [6][7][8] In particular, Picard et al suggested that the high field stress test could be used as a device selection technique for the radiation environment without an actual radiation test. [5][6][7][8] Schwalke et al used the high field stress test as an accelerated reliability testing method for the gate oxide.…”

Section: Introductionmentioning

confidence: 99%

A comparison of ionizing radiation and high field stress effects in n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors

Park

Wie

2004

Journal of Applied Physics

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Articles you may be interested inCross-sectional dopant profiling and depletion layer visualization of SiC power double diffused metal-oxidesemiconductor field effect transistor using super-higher-order nonlinear dielectric microscopy A methodology to identify and quantify mobility-reducing defects in 4H-silicon carbide power metal-oxidesemiconductor field-effect transistors Influence of bulk bias on negative bias temperature instability of p -channel metal-oxide-semiconductor fieldeffect transistors with ultrathin SiON gate dielectrics J. Appl. Phys. 99, 064510 (2006); 10.1063/1.2183409 Drive current enhancement in p -type metal-oxide-semiconductor field-effect transistors under shear uniaxial stress Appl. Phys. Lett. 85, 6188 (2004); 10.1063/1.1841452Analysis of postirradiation annealing of n-channel power vertical double-diffused metal-oxide-semiconductor transistors n-channel power vertical double-diffused metal-oxide-semiconductor field-effect-transistor (VDMOSFET) devices were subjected to a high electric field stress or to a x-ray radiation. The current-voltage and capacitance-voltage measurements show that the channel-side interface and the drain-side interface are affected differently in the case of high electric field stress, whereas the interfaces are nearly uniformly affected in the case of x-ray radiation. This paper also shows that for the gated diode structure of VDMOSFET, the direct-current current-voltage technique measures only the drain-side interface; the subthreshold current-voltage technique measures only the channel-side interface; and the capacitance-voltage technique measures both interfaces simultaneously and clearly distinguishes the two interfaces. The capacitance-voltage technique is suggested to be a good quantitative method to examine both interface regions by a single measurement.

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“…With increasing utilization of MOS technology for the realization of power devices and ICs, the interest in ultrathick gate oxides has steadily grown, and investigations of related reliability issues have recently gained in importance [6][7][8][9]. Investigations by Picard et al [6,7] have indicated the existence of similar effects of gate bias stress and ionising radiation on electrical parameters of power VDMOSFETs, but their analysis of responsible mechanisms has remained in the scope of qualitative description. Actually, their work was aimed at utilizing the gate bias stress for radiation hardening of VDMOSFETs [6] and developing the device selection method for application in radiation environment [7].…”

Section: Introductionmentioning

confidence: 99%

“…Investigations by Picard et al [6,7] have indicated the existence of similar effects of gate bias stress and ionising radiation on electrical parameters of power VDMOSFETs, but their analysis of responsible mechanisms has remained in the scope of qualitative description. Actually, their work was aimed at utilizing the gate bias stress for radiation hardening of VDMOSFETs [6] and developing the device selection method for application in radiation environment [7]. The former idea seems to be inapplicable, while the latter one sounds promising; in both cases, detailed analysis of mechanisms responsible for behaviour of device parameters during stressing [10] and subsequent spontaneous recovery is required.…”

Section: Introductionmentioning

confidence: 99%

Spontaneous recovery of positive gate bias stressed power VDMOSFETs

Stojadinović

Manić

Djorić-Veljković

et al.

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)

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Spontaneous recovery of threshold voltage and channel carrier mobility in positive gate bias stressed power VDMOSFETs and the underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. Electron tunneling from neutral oxide traps associated with trivalent silicon ≡Si o • defects into the oxide conduction band is proposed as the main mechanism responsible for stress-induced buildup of positive oxide-trapped charge. Subsequent hole tunneling from the charged oxide traps ≡Si o + to interface-trap precursors ≡Si s −Η is proposed as the dominant mechanism responsible for the interface trap buildup. A chain of mechanisms related to a presence of hydrogen species is proposed in order to explain changes of oxide-trapped charge and interface trap densities during the spontaneous recovery. Interface trap ≡Si s • passivation due to their reaction with hydrogen atoms is proposed as a main mechanism responsible for a decrease of interface trap density. Hydrogen molecule cracking at charged oxide traps ≡Si o + , which leads to their neutralization, is proposed as the dominant mechanism responsible for a decrease of oxide-trapped charge density.

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Use of electrical stress and isochronal annealing on power MOSFETs in order to characterize the effects of 60 Co irradiation

Cited by 36 publications

References 9 publications

Physico-chemical processes in metal–oxide–semiconductor transistors with thick gate oxide during high electric field stress

Physico-chemical processes in metal–oxide–semiconductor transistors with thick gate oxide during high electric field stress

A comparison of ionizing radiation and high field stress effects in n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors

Spontaneous recovery of positive gate bias stressed power VDMOSFETs

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