Use of high order precursors for manufacturing gate all around devices

Hikavyy, Andriy; Zyulkov, Ivan; Mertens, Hans; Witters, L.; Loo, Roger; Horiguchi, N.

doi:10.1016/j.mssp.2016.10.044

Cited by 32 publications

(39 citation statements)

References 13 publications

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“…12). 43 The Ge/Si 0.35 Ge 0.65 layers are grown on Si 0.3 Ge 0.7 step graded SRBs. The slightly higher Ge content in the SRB with respect to the SiGe in the multi-stack leads to a slight reduction of the lattice mismatch between the strained Ge and the virtual substrate.…”

Section: In Ref 2)mentioning

confidence: 99%

Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

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Section: In Ref 2)mentioning

confidence: 99%

Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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“…The epi reactors are equipped with conventional and high order Si and Ge precursors for lower temperature processes. 6 The choice of precursors will be discussed in the relevant sections of the paper. P and n-type dopants are provided to the growth chemistry through the use of diborane (B 2 H 6 ), arsine (AsH 3 ) and phosphine (PH 3 ).…”

Section: Epitaxy For Channel and Source/drain Materialsmentioning

confidence: 99%

“…Tall fins with high aspect ratio are now considered to maximize drive currents and Surrounded-Gate Transistors (SGT) or Gate-All-Around (GAA) devices are being investigated as an ultimate extension of FinFETs. 3 From the materials side, complementary to Si, SiGe and Ge are evaluated as high mobility channel materials 2,[4][5][6][7] and Source/Drain (S/D) stressor layers are employed to enhance channel mobility and reduce S/D contact resistance. 5,[8][9][10] Working with these geometries and materials sets different requirements for the epitaxial growth steps in device fabrication.…”

mentioning

confidence: 99%

Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

Porret

Hikavyy

Granados

et al. 2019

ECS J. Solid State Sci. Technol.

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As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

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“…NW FETs are extremely scaled FinFETs [51], [52]. In this case, the channel is fabricated either on an SOI substrate, or free standing by isotropic etching followed by deposition of the gate dielectric and the metal gate [ Fig.…”

Section: Nanowires and 3-d Stackingmentioning

confidence: 99%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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-From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.Index Terms-2-D semiconductor, carbon, CMOS, deep submicrometer, FinFET, graphene, MoS2, resistive random access memory (RRAM), silicon-on-insulator (SOI), thin film, total ionizing dose (TID), ultrathin buried oxide (UTBOX).

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Use of high order precursors for manufacturing gate all around devices

Cited by 32 publications

References 13 publications

Processing Technologies for Advanced Ge Devices

Processing Technologies for Advanced Ge Devices

Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

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