Used self-controllable voltage level technique to reduce leakage current in DRAM 4×4 in VLSI

Estimation of High Performance 3T DRAM Cell at Nanometer Technology

“…In the proposed schematic of 3T DRAM the switching transistor is NM 1 and NM 3 connected with the bit line and bit bar line respectively, To perform the "write" operation, the write word line is enabled 1 or high therefore the transistor NM 1 is turned "on" then the voltage of the bit line is passed on to the storage transistor NM 2 , data is stored in the junction capacitance of the transistor and the voltage of the bit line bar is discharged to the ground and hence write operation is performed [4,5]. During the read operation read word line is enabled or high, the gate voltage of storage transistor is high and the transistor NM 2 and NM 3 both are turned on.…”

“…There are three transistors M 1 , M 2 , M 3 are connected, only one single transistor NM 2 utilise as the working transistor to store the information data. The other two transistor NM 1 and NM 3 are used as access switches, according to write and read operation respectively [4].…”