Using cap-integral standoffs to reduce chip hot-spot temperatures in electronic packages

June, Michael Sean; Sikka, Kamal

doi:10.1109/itherm.2002.1012454

Cited by 7 publications

(5 citation statements)

References 2 publications

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“…Warnock et al [21] described the IBM POWER4 dual-core processor design and thermal modeling results, where the data cache and the fixed-point arithmetic units were identified as the hottest regions. Related analyses and investigations in modeling nonuniform power dissipation can also be found in [22][23][24].…”

Section: Characteristics Of Cpu Power Dissipationmentioning

confidence: 99%

Challenges in Cooling Design of CPU Packages for High-Performance Servers

Wei

2008

Heat Transfer Engineering

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Cooling technologies that address high-density and asymmetric heat dissipation in CPU packages of high-performance servers are discussed. Thermal management schemes and the development of associated technologies are reviewed from a viewpoint of industrial application. Particular attention is directed to heat conduction in the package and heat removal from the package/heat sink module. Power dissipation and package cooling characteristics of high-performance microprocessors are analyzed. The development of a new metallic thermal interface technology is introduced, where thermal and mechanical performance of an indium-silver alloy in the chip/heat spreader assembly was studied. The paper also reports on research on other thermal management materials, such as diamond composite heat-spreading materials. Some actual package designs are described to illustrate the enhanced heat spreading capability of heat pipes and vapor chambers.

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Section: Characteristics Of Cpu Power Dissipationmentioning

confidence: 99%

Challenges in Cooling Design of CPU Packages for High-Performance Servers

Wei

2008

Heat Transfer Engineering

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“…Previous work has been done in understanding the thermal solutions for the nonuniform power distribution within the silicon die. Some of the previous work includes Goh et al [9] using genetic algorithm approach, Getkin et al [10] using simplified fin modeling approach, Sikka et al [11] using analytical temperature distribution method, June et al [12] using cap-integral standoffs, Yu et al [13] using fast placement dependent full chip thermal simulations .…”

Section: Background and Motivationmentioning

confidence: 99%

Multi-Objective optimization entailing computer architecture and thermal design for non-uniformly powered microprocessors

Raju

Kaisare

Agonafer

et al. 2008

2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. A lot of work has been done addressing this issue with a need of thermally aware computer architecture with a concurrent design approach based on thermal and device clock performance. Previous work has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniformly powered functional blocks with different power matrices. The study also provided design guidelines to minimize thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. This analysis, however, had no constraints placed on the redistribution of functional blocks regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements.In this study, numerical model is developed that utilizes multi-objective optimization consists of redistribution of functional blocks to both improve device performance and thermal performance. Previously developed design guideline for thermal optimization is used as a base line case. This baseline case is embedded into computer architecture (floor Plan) to develope a compact model satisfying both electrical and thermal performance. Constraints for the electrical optimization are regarding the maximum separation of any 2 (or more) functional blocks. Once positioning of the functional blocks is carried out, thermal optimization of these nonuniformly powered functional blocks is carried out to minimize thermal resistance. This process is repeated until you get both improve device performance and thermal performance for the non-uniformly powered microprocessor. Finally recommendations are provided for an architecture design regarding maximum separation of functional block with minimum thermal resistance.

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“…The Stefan's squeeze-flow equation is expanded to include the flow resistance of the paste as it is squeezed through the channels. The resistance to flow or pressure drop generated by a Newtonian liquid flowing in a channel is described by the Hagen-Poiseuille equation (3) where is the volume squeeze rate, is the length of the capillary, is the dynamic viscosity, and is the effective hydrodynamic radius which is for a rectangular channel with , . The effective hydrodynamic radius is dominated by the smaller rectangular channel dimension [15].…”

Section: Squeeze Flow and Poiseuille Flow Theorymentioning

confidence: 99%

“…Advantages of thermal pastes are their low cost, ease of assembly, and re-workability; disadvantages are the large thermal resistance and the susceptibility for voiding and drying out [1], [2]. Millimeter-sized protrusions or standoffs allow an improved cooling at localized areas of overheat [3], [4] while not degrading the overall lifetime of the TIM. They perform better because good thermal contact through paste or adhesive is easy to obtain on small areas.…”

mentioning

confidence: 99%

Hierarchically Nested Channels for Fast Squeezing Interfaces With Reduced Thermal Resistance

Brunschwiler

Kloter

Linderman

et al. 2007

IEEE Trans. Comp. Packag. Technol.

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We report on a simple method to improve bondline formation kinetics by means of a hierarchical set of channels patterned into one of the surfaces. The channel arrays are used to improve the gap squeezing and cooling of single and multiple flip-chip electronic modules with highly viscous fluids and thermal pastes or greases. They allow a fast formation of thin gaps or bond lines by reducing the pressure gradient in the thermal interface material as it moves in and out of the gap. Models describing the dynamics of Newtonian fluids in these "hierarchically nested channel" interfaces combine squeeze flow and Hagen-Poiseuille theories. Rapid bond-line formation is demonstrated for Newtonian fluids and selected particle-filled pastes. Modeling of particle-laden polymeric pastes includes Bingham and Hershel-Bulkley fluid properties. Bond-line formation and thermal resistance are improved particularly for high-viscosity high-thermal-conductivity interface materials created from higher-volumetric particle loadings or for thermal interface materials with smaller filler-particle diameters.Index Terms-Bondline thickness (BLT), fluid flow, interface, interface aging, microchannel, packaging, thermal interface material (TIM), thermal management, thermal resistance, viscosity.

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Using cap-integral standoffs to reduce chip hot-spot temperatures in electronic packages

Cited by 7 publications

References 2 publications

Challenges in Cooling Design of CPU Packages for High-Performance Servers

Challenges in Cooling Design of CPU Packages for High-Performance Servers

Multi-Objective optimization entailing computer architecture and thermal design for non-uniformly powered microprocessors

Hierarchically Nested Channels for Fast Squeezing Interfaces With Reduced Thermal Resistance

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