Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. A lot of work has been done addressing this issue with a need of thermally aware computer architecture with a concurrent design approach based on thermal and device clock performance. Previous work has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniformly powered functional blocks with different power matrices. The study also provided design guidelines to minimize thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. This analysis, however, had no constraints placed on the redistribution of functional blocks regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements.In this study, numerical model is developed that utilizes multi-objective optimization consists of redistribution of functional blocks to both improve device performance and thermal performance. Previously developed design guideline for thermal optimization is used as a base line case. This baseline case is embedded into computer architecture (floor Plan) to develope a compact model satisfying both electrical and thermal performance. Constraints for the electrical optimization are regarding the maximum separation of any 2 (or more) functional blocks. Once positioning of the functional blocks is carried out, thermal optimization of these nonuniformly powered functional blocks is carried out to minimize thermal resistance. This process is repeated until you get both improve device performance and thermal performance for the non-uniformly powered microprocessor. Finally recommendations are provided for an architecture design regarding maximum separation of functional block with minimum thermal resistance.

Telecommunication cabinets house numerous electronic components which dissipate heat to varying degrees. The thermal management of these components is of utmost importance in the design of these cabinets. CFD allows designers to try out and compare various cabinet configurations and enable an optimal design thus reducing unnecessary construction of cabinet prototypes and elaborate experimental tests, thereby resulting in cost savings and reduction in the lead time.This paper deals with design and thermal analysis of a CommScope outdoor integrated telecommunication enclosure, named RBA84-3036. This cabinet is air-cooled by a series of DC axial door mounted fans. Various design and cooling configurations will have to be considered and verified to meet the tight thermal requirements within the enclosure. NomenclaturePS in -DC power shelf inlet temperature PS out -DC power shelf outlet temperature Cust in -Customer electronic unit inlet temperature Cust out -Customer electronic unit outlet temperature

The static power consumption due to leakage current plays a significant part in semiconductor devices, as the device dimensions continue to shrink. Low power dissipation is one of the critical factors needed to achieve high performance in a chip. New methods are continuously being implemented for reduction of leakage current in deep sub micron ultra thin SOI MOSFET using device simulator tools. In this paper, an 18nm gate length ultra thin SOI MOSFET is simulated for different silicon body thicknesses and the leakage current is determined by using the device simulator, MEDICITM. It is demonstrated that MEDICI™ device simulations is a good tool that can effectively be used for ultra thin SOI MOSFET devices to study the effect of design parameters on the leakage current. Ultra thin SOI MOSFET with 18nm gate length of different Silicon body thickness is simulated and the leakage current as determined by using MEDICI™ shows that the leakage current decreases by 10–15% as the silicon body thickness reduces by 2 nm.