Using design patterns to overcome image processing constraints on FPGAs

Gribbon, K.T.; Bailey, Donald G.; Johnston, C.T.

doi:10.1109/delta.2006.93

Cited by 14 publications

(4 citation statements)

References 12 publications

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“…The proposed architecture is capable of producing one edge-pixel every clock cycle. The work in [18] illustrated how to use design patterns in the mapping process to overcome image processing constraints on FPGAs. However, most of the previous works, for example, [16][17][18], only focused on the algorithms alone and did not consider the platform characteristics as a factor in the design.…”

Section: Related Workmentioning

confidence: 99%

Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

Huang

Serres

El‐Ghazawi

et al. 2010

International Journal of Reconfigurable Computing

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Reconfigurable Computers (RCs) with hardware (FPGA) co-processors can achieve significant performance improvement compared with traditional microprocessor (μP)-based computers for many scientific applications. The potential amount of speedup depends on the intrinsic parallelism of the target application as well as the characteristics of the target platform. In this work, we use image processing applications as a case study to demonstrate how hardware designs are parameterized by the co-processor architecture, particularly the data I/O, i.e., the local memory of the FPGA device and the interconnect between the FPGA and theμP. The local memory has to be used by applications that access data randomly. A typical case belonging to this category is image registration. On the other hand, an application such as edge detection can directly read data through the interconnect in a sequential fashion. Two different algorithms of image registration, the exhaustive search algorithm and the Discrete Wavelet Transform (DWT)-based search algorithm, are implemented on hardware, i.e., Xilinx Vertex-IIPro 50 on the Cray XD1 reconfigurable computer. The performance improvements of hardware implementations are10×and2×, respectively. Regarding the category of applications that directly access the interconnect, the hardware implementation of Canny edge detection can achieve544×speedup.

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Section: Related Workmentioning

confidence: 99%

Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

Huang

Serres

El‐Ghazawi

et al. 2010

International Journal of Reconfigurable Computing

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“…ROF are a class of spatial filtering algorithms which deal with pixel operation functions which are often regular and fine grain and hence well suited for hardware implementations [4] especially on FPGAs [5,22] as their physical structure allows exploiting the inherent spatial and temporal parallelism of low level image processing applications [6,7,23]. ROF's can be implemented efficiently on FPGAs because they rely on Boolean operations rather then arithmetic operations [24].…”

Section: Introductionmentioning

confidence: 99%

Implementation and analysis of optimized architectures for rank order filter

Meena

Kulkarni

2007

J Real-Time Image Proc

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In this paper we present two architectures based on the replication sort algorithm (RSA) and rank based network sorting algorithm (RBNS) for implementation of Rank order filer (ROF). This paper focuses on optimization strategies for sorting in terms of operating speed (throughput) and area (no. of comparators). The RSA algorithm achieves maximum throughput by sorting, which finds the position of all the window elements in parallel using eight bit comparators, a LUT to store the bit sum and a decoder. The time cost for filtering the complete image remains constant irrespective of the size of the window and the algorithm is generalized for all rank orders. The RBNS architecture is based on Sorting Network architecture algorithm, optimized for each desired output rank with O (N) hardware complexity compared to O (N 2 ) complexity of the existing architectures that are based on bubble-sort and quick-sort reported so far. The proposed architectures use the concepts of pipelining and grain level parallelism and accomplish the task of sorting and filtering each sample appearing at the input window of the filter in one clock cycle, excluding the initial latency.

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“…Programming an FPGA is significantly different from writing software for conventional systems with a single processor. In designing an appropriate algorithm for FPGAs, it is necessary to take into account limited memory bandwidth, parallel operations, pipelining and resource conflicts [2].…”

Section: Introductionmentioning

confidence: 99%

Towards a visual notation for pipelining in a visual programming language for programming FPGAs

Johnston¹,

Bailey²,

Lyons³

2006

Proceedings of the 6th ACM SIGCHI New Zealand Chapter's International Conference on Computer-Human Interaction Design Centered

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VERTIPH is a visual language designed to aid in the development of image processing algorithms on FPGAs (Field Programmable Gate Arrays). We justify the use of a visual language for this purpose, and describe the key parts of VERTIPH. One aspect of importance is how to clearly and efficiently represent a pipeline of processors, and in particular distinguish a pipeline from the simpler serial or parallel structures. This paper develops a number of pipeline representations, discussing the rationale behind and limitations associated with each representation. The culmination of this development is the Sequential Pipeline with Detailed Bars, visually an efficient and unambiguous representation.

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Using design patterns to overcome image processing constraints on FPGAs

Cited by 14 publications

References 12 publications

Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study

Implementation and analysis of optimized architectures for rank order filter

Towards a visual notation for pipelining in a visual programming language for programming FPGAs

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