Using Scan-Dump Values to Improve Functional-Diagnosis Methodology

Vimjam, V.C.; Amyeen, Enamul; Guo, Ruifeng; Venkataraman, S.; Hsiao, Michael S.; Yang, Kai

doi:10.1109/vts.2007.88

Cited by 8 publications

(4 citation statements)

References 11 publications

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“…We will illustrate the trace signal selection method using the following example. Let us consider a circuit with three flipflops f 1, f 2, f 3 and five gates g 1 , g 2 , g 3 , g 4 , g 5 . Suppose we obtain the following information from the implication graph:…”

Section: New Trace Signal Selectionmentioning

confidence: 99%

“…In [6] and [7], the authors discuss post-processing algorithms which can be used to identify the failing state elements from the scan dump data. In [5] a method was proposed which utilizes backward and forward logic implications of the scan-dump values to restore more circuit gate values. However, the main disadvantage of the scan-based approaches is the repeated scan-dumps.…”

Section: Introductionmentioning

confidence: 99%

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Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug

Prabhakar

Hsiao

2009

2009 Asian Test Symposium

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An effective silicon debug technique uses a trace buffer to monitor and capture a portion of the circuit response during its functional, post-silicon operation. Due to the limited space of the available trace buffer, selection of the critical trace signals plays an important role in both minimizing the number of signals traced and maximizing the observability/restorability of other untraced signals during post-silicon validation. This paper presents a new method for trace buffer signal selection for the purpose of post-silicon debug. The selection is performed by favoring those signals with the most number of implications that are not implied by other signals. Then, based on the values of the traced signals during silicon debug, we introduce an algorithm which uses a SAT-based multi-node implication engine to restore the values of untraced signals across multiple time-frames.Experimental results for sequential benchmark circuits showed that the proposed approach selects the trace signals effectively, giving a high restoration percentage compared with other techniques.

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Section: New Trace Signal Selectionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug

Prabhakar

Hsiao

2009

2009 Asian Test Symposium

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“…For example, scan dumps can be compared automatically between good and bad runs to help root-cause a fault [2], or propagated forward and backward to help improve visibility and diagnosis [10]. A binary-search-based debug method [12] iteratively divides the search space in half until the method identifies the first cycle in which the error is activated and observed.…”

mentioning

confidence: 99%

“…In contrast to [2,10,12], our method handles non-determinism in the system execution. 1 Unlike [8], our method is not processor-specific and can be applied to any design.…”

mentioning

confidence: 99%

Lazy suspect-set computation

Sengupta

Paula

et al. 2012

Proceedings of the Great Lakes Symposium on VLSI

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Current silicon test methods are highly effective at sensitizing and propagating most electrical faults. Unfortunately, with ever increasing chip complexity and shorter time-tomarket windows, an increasing number of faults escape undetected. To address this problem, we propose a novel technique to help identify hard-to-find electrical faults that are not detected using conventional test methods, but manifest themselves as observable functional errors during functional test, system test, or during actual use in the field. These faults are too sequentially deep to be diagnosed using simulation, ATPG, or formal tools. Our technique relies on repeated full-speed chip runs that witness the functional bug, combined with some additional on-chip functional debug support and off-line analysis, to compute a possible set of suspected faults. The technique quickly prunes the suspect set, and for each suspect, it can provide a short test vector for further analysis. Experiments on the ITC'99 benchmarks demonstrate the effectiveness of our approach.

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Dataset development of GPU block using Scan Dump for Silicon Debug

Kulkarni¹,

Aradhya²

2021

2021 6th International Conference on Communication and Electronics Systems (ICCES)

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Using Scan-Dump Values to Improve Functional-Diagnosis Methodology

Cited by 8 publications

References 11 publications

Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug

Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug

Lazy suspect-set computation

Dataset development of GPU block using Scan Dump for Silicon Debug

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