Using Wavelet Transform and Partial Distance Search to Implement kNN Classifier on FPGA with Multiple Modules

Li, Hui-Ya; Yeh, Yao-Jung; Hwang, Wen-Jyi

doi:10.1007/978-3-540-74260-9_98

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…The proposed architecture also can apply to applications which perform specific operations on k targets found within the input set. As compared to architectures in [ 12 , 32 ] and [ 33 ] for the k NN application, the proposed architecture takes advantage of the pipeline fashion to have higher throughput even though these architectures have same latency of picking out k winners.…”

Section: Resultsmentioning

confidence: 99%

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Hwang

2012

Sensors

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A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.

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Section: Resultsmentioning

confidence: 99%

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Hwang

2012

Sensors

Self Cite

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“…Among them, concerning the studies for classifiers, e.g., [1]- [4] uses the technics of artificial neural networks. Another studies, e.g., [5]- [8] uses the other technics such as the AdaBoost algorithm, the wavelet transform and the nearest neighbor. In addition, most of them are based on complicated sequential circuits such as a combination of a microprocessor and a kilo-byte RAM.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-based fast classifier with high generalization property

Horita

Takanami²

2010

SIGARCH Comput. Archit. News

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This paper proposes a scheme to implement classifiers with high generalization properties on FPGAs. The classifiers consist of only combinational logic circuits, which are based on a simple concept, and the VHDL source files which describe the classifiers are generated by a C-language function, tuning VHDL notations for adders in them to reduce both its hardware size and computation time. Simulation results based on a character recognition are shown in terms of generalization property, hardware size, computation time, and electricity consumption.

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The implementation of a KNN classifier on FPGA with a parallel and pipelined architecture based on Predetermined Range Search

Tian

Wang

Zhang

et al. 2016

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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Using Wavelet Transform and Partial Distance Search to Implement kNN Classifier on FPGA with Multiple Modules

Cited by 3 publications

References 6 publications

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

An FPGA-based fast classifier with high generalization property

The implementation of a KNN classifier on FPGA with a parallel and pipelined architecture based on Predetermined Range Search

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