Vacuum underfill technology for advanced packaging

Horibe, Akihiro; Paquet, M.-C.; Gaynes, Michael; Feger, C.; Sakuma, Katsuyuki; Knickerbocker, John; Orii, Yasumitsu; Hoshiyama, Masaaki; Hasegawa, Masahiro; Sato, Toshiyuki; Yoshii, H.; Сузукі, Осаму; Kotaka, K.; Nagasaka, T.; Terada, Kenji; Ishikawa, Kōji; Hirayama, Y.

doi:10.1109/ectc.2011.5898632

Cited by 2 publications

(2 citation statements)

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“…Post-applied methods [14][15][16][17][18][19] develop on the basis of process and typically utilize dispensing or molding technique to underfill an assembled package. A dominant benefit for post-applied methods is entirely compatibility with current existing SMT facilities.…”

Section: Introductionmentioning

confidence: 99%

“…A dominant benefit for post-applied methods is entirely compatibility with current existing SMT facilities. A vacuum capillary underfill (VCUF) introduced by IBM [14,15] employs a low-volatile material to underfill a 3D chip stack. VCUF can be considered as an evolvement of the 2D conventional underfill since the material is dispensed along chip edges in a vacuum-assisted dispensing system.…”

Section: Introductionmentioning

confidence: 99%

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3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

Le¹,

Lee²,

Zhang³

2017

J. Micromech. Microeng.

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3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%