Van der Waals negative capacitance transistors

Wang, Xiaowei; Yu, Peng; Lei, Zhendong; Cao, Xun; Liu, Fucai; You, Lü; Zeng, Qingsheng; Deng, Ya; Zhu, Chao; Zhou, Jiadong; Fu, Qundong; Wang, Junling; Huang, Yizhong; Liu, Zheng

doi:10.1038/s41467-019-10738-4

Cited by 195 publications

(188 citation statements)

References 36 publications

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“…), or 1D (such as carbon nanotube (CNT), graphene nanoribbon (GNR) etc. ), generating numerous "NC-FETs" in the past several years [8][9][10][11][12][13][14][15] . However, none of them exhibit SSs that are noticeably smaller than 60 mV per decade and simultaneously free of hysteresis during both AC and DC operations (see Supplementary Table 1).…”

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confidence: 99%

Is negative capacitance FET a steep-slope logic switch?

2020

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The negative-capacitance field-effect transistor(NC-FET) has attracted tremendous research efforts. However, the lack of a clear physical picture and design rule for this device has led to numerous invalid fabrications. In this work, we address this issue based on an unexpectedly concise and insightful analytical formulation of the minimum hysteresis-free subthreshold swing (SS), together with several important conclusions. Firstly, well-designed MOSFETs that have low trap density, low doping in the channel, and excellent electrostatic integrity, receive very limited benefit from NC in terms of achieving subthermionic SS. Secondly, quantumcapacitance is the limiting factor for NC-FETs to achieve hysteresis-free subthermionic SS, and FETs that can operate in the quantum-capacitance limit are desired platforms for NC-FET construction. Finally, a practical role of NC in FETs is to save the subthreshold and overdrive voltage losses. Our analysis and findings are intended to steer the NC-FET research in the right direction.

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confidence: 99%

Is negative capacitance FET a steep-slope logic switch?

2020

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“…The device shown in Figure 3e has a typical structure of ferroelectric FET for studying the so‐called negative‐capacitance effect. [ 42 ] While measuring the transfer curve of the device, three types of capacitors are involved and the corresponding capacitances are (left part in Figure 1d): gate insulator capacitance (C i ), here it is a series connection of ferroelectric capacitor (here CIPS) and h‐BN capacitor, and channel capacitance (here MoS 2 , C c ). It has been found that when the capacitance parameters satisfy the condition | C i | > C c , a dielectric matching can be reached, and the hysteresis in the I DS – V GS curve is absent.…”

Section: Figurementioning

confidence: 99%

Gate‐Coupling‐Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in Van der Waals Ferroelectric Heterojunctions

et al. 2020

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Ferroelectric field‐effect transistors (FeFETs) are one of the most interesting ferroelectric devices; however, they, usually suffer from low interface quality. The recently discovered 2D layered ferroelectric materials, combining with the advantages of van der Waals heterostructures (vdWHs), may be promising to fabricate high‐quality FeFETs with atomically thin thickness. Here, dual‐gated 2D ferroelectric vdWHs are constructed using MoS2, hexagonal boron nitride (h‐BN), and CuInP2S6 (CIPS), which act as a high‐performance nonvolatile memory and programmable rectifier. It is first noted that the insertion of h‐BN and dual‐gated coupling device configuration can significantly stabilize and effectively polarize ferroelectric CIPS. Through this design, the device shows a record‐high performance with a large memory window, large on/off ratio (107), ultralow programming state current (10−13 A), and long‐time endurance (104 s) as nonvolatile memory. As for programmable rectifier, a wide range of gate‐tunable rectification behavior is observed. Moreover, the device exhibits a large rectification ratio (3 × 105) with stable retention under the programming state. This demonstrates the promising potential of ferroelectric vdWHs for new multifunctional ferroelectric devices.

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“…Copper indium thiophosphate, CuInP 2 S 6 (CIPS), a van der Waals (vdW) layered material that is ferrielectric at room temperature [20][21][22][23][24] has been explored for NC due to its compatibility with other 2D materials for advanced heterostructures. [25] The polarization of CIPS arises from the noncentrosymmetric z displacement of Cu and In atoms with respect to the P 2 S 6 sublattice. [26,27] Recently, density functional theory (DFT) demonstrated the presence of two iso-symmetric polar phases.…”

Section: Introductionmentioning

confidence: 99%

The Concept of Negative Capacitance in Ionically Conductive Van der Waals Ferroelectrics

Neumayer

Lei

O’Hara

et al. 2020

Advanced Energy Materials

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Negative capacitance (NC) provides a path to overcome the Boltzmann limit that dictates operating voltages in transistors and, therefore, may open up a path to the challenging proposition of lowering energy consumption and waste heat in nanoelectronic integrated circuits. Typically, NC effects in ferroelectric materials are based on either stabilizing a zero‐polarization state or slowing down ferroelectric switching in order to access NC regimes of the free‐energy distribution. Here, a fundamentally different mechanism for NC, based on CuInP2S6, a van der Waals layered ferrielectric, is demonstrated. Using density functional theory and piezoresponse force microscopy, it is shown that an unusual combination of high Cu‐ion mobility and its crucial role in determining polarization magnitude and orientation (P) leads to a negative slope of the polarization versus the electric field E, dP/dE < 0, which is a requirement for NC. This mechanism for NC is likely to occur in a wide class of materials, offering new possibilities for NC‐based devices. The nanoscale demonstration of this mechanism can be extended to the device‐level by increasing the regions of homogeneous polarization and polarization switching, for example, through strain engineering and carefully selected electric field pulses.

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Van der Waals negative capacitance transistors

Cited by 195 publications

References 36 publications

Is negative capacitance FET a steep-slope logic switch?

Is negative capacitance FET a steep-slope logic switch?

Gate‐Coupling‐Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in Van der Waals Ferroelectric Heterojunctions

The Concept of Negative Capacitance in Ionically Conductive Van der Waals Ferroelectrics

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