Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

“…This can be seen from the range of the data at a given dose, as well as the relative standard deviation (RSD). Variations in quantities such as doping concentration, transistor width, STI topology (planarity), and STI stress resulting from the contributions of process steps such as liner oxidation, high density-plasma oxide deposition, thermal oxidation processes after STI formation, and corner rounding effects in the STI [2][3][4][5][6][7][12][13][14][15] may contribute to the device-to-device variability as the dose increases.…”

“…Device-to-device variability between nominally identical devices and systematic variability that depends on the local structure can affect circuit-level degradation [1,2]. As the technology scales, the pre-irradiation off-state (V g = 0) current mechanisms can change from being dominated by junction or sidewall leakage to being dominated by channel subthreshold current.…”

Statistical aspects of NBTI/PBTI and impact on SRAM yield

“…The major sources of statistical variability in conventional (bulk) MOSFETs include random discrete dopants (RDD) [1], line edge roughness (LER) [2] and poly-silicon granularity [3]. Statistical variability approaches more than 50% of the total variability in the 45 nm technology generation [4] and is becoming the dominant component of the variability at the 32 nm technology generation [5].…”

Impact of context dependenent variability in CMOS embedded with SiGe on circuit performance & power

“…Consequently, larger margins are required and thus performance benefits derived from scaling are reduced [4][5]. While both the random (process related) and systematic (design related) sources are of interest, the modulation of transistors with its varying context (layout) have a more direct impact on power consumption and timing of complex circuits [5][6].…”

“…Monte Carlo sweeps over a wide range of chosen devices parameters can be run that results in a distribution of design constraints such as circuit delay or noise margin. In case of stress as a process variant, both Kahng [6] and Aikawa [5] have modified BSIM SPICE models by accounting for the mobility parameter.…”