Variability study with CD-SEM metrology for STT-MRAM: correlation analysis between physical dimensions and electrical property of the memory element

Ohashi, T.; Yamaguchi, Atsuko; Hasumi, Kazuhisa; Ito, Osamu; Ikota, Masami; Lorusso, Gian; Donadio, Gabriele Luca; Yasin, F.; Rao, Siddharth; Kar, Gouri Sankar

doi:10.1117/12.2257908

Cited by 6 publications

(4 citation statements)

References 6 publications

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“…Extensive Monte Carlo (MC) simulations were carried out at the operating temperature of 77 K, while considering the effect of both DMTJ and CMOS process variability. For the DMTJ device, Gaussiandistributed variations were considered with a variability (σ/µ) of 5% for the cross-section area and 1% for t OX,T , t OX,B , and t FL , in line with state-of-the-art literature [8,[34][35][36][37][38]. Fig.…”

Section: Bitcell-level Simulation Resultsmentioning

confidence: 99%

Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs

Garzón,

De Rose,

Crupi

et al. 2022

Preprint

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This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnel junctions (DMTJs) for energy-efficient spin-transfer torque magnetic random access memories (STT-MRAMs) operating at the liquid nitrogen boiling point (77 K). Our study is carried out through a macrospin-based Verilog-A compact model of DMTJ, along with a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. Comprehensive bitcell-level electrical characterization is used to estimate the energy/latency per operation and leakage power at the memory architecture-level. As a main result of our analysis, we show that energy-efficient small-to-large embedded memories can be obtained by significantly relaxing the non-volatility requirement of DMTJ devices at room temperature (i.e., by reducing the cross-section area), while maintaining the typical 10-years retention time at cryogenic temperatures. This makes DMTJ-based STT-MRAM operating at 77 K more energy-efficient than sixtransistors static random-access memory (6T-SRAM) under both read and write accesses (-56% and -37% on average, respectively). Obtained results thus prove that DMTJ-based STT-MRAM with relaxed retention time is a promising alternative for the realization of reliable and energyefficient embedded memories operating at cryogenic temperatures.

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Section: Bitcell-level Simulation Resultsmentioning

confidence: 99%

Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs

Garzón,

De Rose,

Crupi

et al. 2022

Preprint

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“…Moreover, to be compatible with the considered transistor devices, the resistance-area product (RA) was set below 10 Ω µm 2 , which is consistent to the trend reported in [7]. In the following analysis, we have also taken into account the effect of process variability on DMTJ devices, by considering Gaussian-distributed variations, with σ/µ equal to 5% for the cross-section area and to 1% for both the FL thickness (t FL ) and oxide barrier thicknesses (t OX,T and t OX,B ) [37][38][39].…”

Section: Double-barrier Magnetic Tunnel Junction (Dmtj)mentioning

confidence: 90%

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

et al. 2021

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Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 V), while showing energy savings of 50% and faster write switching of 60%.

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“…Originally, it was proposed by Chen and Parkin in [28] that the read operation can be performed by affixing a magnetoresistive sensor in proximity to the track in order to use the emanating fringing fields for distinguishing between the magnetic states, or by integrating an MTJ sensor directly onto the racetrack [4]. Recent developments in MTJs [29], [30] allow for CMOS integration and scaling to feature sizes compatible with RTM applications. Furthermore, TMR values can far exceed those of GMR reaching values upward of 600% at room temperature [31], [32].…”

Section: B Read/write Mechanism In Rtmmentioning

confidence: 99%

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade

et al. 2020

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| Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the potential to overcome fundamental constraints of existing memory and storage devices. It is unique in that its core differentiating feature is the movement of data, which is composed of magnetic domain walls (DWs), by short current pulses. This enables more data to be stored per unit area compared to any other current technologies. On the one hand, RTM has the potential for mass data storage with unlimited endurance using considerably less energy than today's technologies. On the other hand, RTM promises an ultrafast nonvolatile memory competitive with static random access memory (SRAM) but with a much smaller footprint. During the last decade, the discovery of novel physical mechanisms to operate RTM has led to a major enhancement in the efficiency with which nanoscopic, chiral DWs can be manipulated. New materials and artificially atomically engineered thin-film structures have been found to increase the speed and lower the threshold current with which the data bits can be manipulated. With these recent Manuscript

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Variability study with CD-SEM metrology for STT-MRAM: correlation analysis between physical dimensions and electrical property of the memory element

Cited by 6 publications

References 6 publications

Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs

Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade

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