Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array

Escudero, M.; Vourkas, Ioannis; Rubio, Antonio; Moll, Francesc

doi:10.1145/3232195.3232213

Cited by 6 publications

(5 citation statements)

References 13 publications

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“…In this work, we build upon ideas commented in [24], [25] and present a crossbar-compatible ratioed logic scheme which is completely variation-tolerant; i.e. it does not suffer from device variability or state drift, and also it does not impact the device endurance as logic operations are performed by just reading the state of memristors acting as inputs.…”

Section: Introductionmentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and in-memory computing. Several memristive logic families have been proposed in the current quest for energy-efficient future computing systems. However, the limited device endurance and variability (both cycleto-cycle and device-to-device) are important parameters to be considered in the assessment of logic operations. In this work we used an accurate physics-based model of a bipolar memristor (supporting parasitics of the device structure and variability of switching voltages and resistance states) and demonstrate that performance of memristor-based in-memory computations can de degraded owing to both variability and state drift impact, if such features are not properly considered in the design flow. Inspired on pseudo-NMOS ratioed logic and based upon a CMOS-like logic scheme, we propose a crossbar-compatible memristive ratioed logic style which is tolerant to device variability and does not affect device endurance as computations do not involve conditional switching of memristors. Using the Cadence Virtuoso suite, we compare this logic scheme with MAGIC and CNIMP approaches, focusing on the universal NOR gate and complex logic functions.

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Section: Introductionmentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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“…The lowest output voltage observed with all-zero inputs (all in HRS) and the highest voltage observed when one input is in logic '1' (LRS), define the voltage range where Vcmp should be located. To be able to implement n-input NOR gates with n > 2, the Vcmp and the value of the RL series resistive element could be reconfigured to guarantee correct functionality of the logic operations [17].…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Thus, any Fig. 1 Circuit schematics for (a,b) memristor ratioed logic (MRL) style OR/AND gate operation with reciprocal resistance switching of memristors [8]; (c) a two-input MAGIC NOR gate with the Op signal activating the logic operation [15]; (d) a two-input ratioed NOR logic gate, implemented according to [17].…”

Section: Introductionmentioning

confidence: 99%

“…Figure 1(d) shows the case of a two-input ratioed NOR gate proposed in [17]. It represents the kind of nonstateful logic schemes where I/O = R/V and logic computations are performed without switching the state of the involved memristors; the latter is beneficial since endurance of memristors can be degraded if logic operations cause frequent switching of the devices.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design and Simulation of Peripheral Driving Circuitry for Computational ReRAM

Fernandez

Vourkas

Rubio

2022

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)

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As an alternative approach to the von Neumann architecture, the notion of computational resistive random-access memory (ReRAM) has emerged, promising faster and more energy-efficient computing systems. In this context, we present a classification of ReRAM-compatible logic design strategies and highlight the potential of nonstateful ratioed logic for computational ReRAM modules. We provide insights towards the design of ad-hoc peripheral circuitry that allows the fusion of memory and ratioed logic operations in the ReRAM module in a reliable manner; i.e., the driving/sensing circuitry allows carrying out memory operations and in-memory multi-level ratioed logic operations. To this end, we present in detail a computational ReRAM driver and focus our description on the operational features that enable memory/logic operations in every row of the crossbar array. We validate circuit functionality through LTSpice simulations for read/write memory and logic operations using a threshold-type bipolar ReRAM device model. The presented practical solutions contribute to the viable development of computational ReRAM.

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“…All simulations were performed in the Cadence Virtuoso suite. The major contributions of this Thesis can be found in relevant publications in [77], [78] and [79].…”

Section: Impact Of Variability In Memristive Logic Inside Crossbar Me...mentioning

confidence: 99%

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

Escudero López

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In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work. Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM.

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Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array

Cited by 6 publications

References 13 publications

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Design and Simulation of Peripheral Driving Circuitry for Computational ReRAM

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

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