Abstract-. In the last years, memristor devices have been proposed as key elements to develop a new paradigm to implement logic gates. In particular, the memristor-based material implication (IMPLY) gate has been presented as a potential powerful basis for logic applications. In the literature, the IMPLY operation has been widely simulated but most of the efforts have been just focused on accomplishing its truth table, only considering the initial and final states of the gate. However, a complete understanding of the time evolution between states is still missing and barely reported yet. In this work, the time evolution of memristor involved in an IMPLY gate are studied in detail for every case of the gate. Furthermore, the impact on IMPLY gate operation of the internal resistor connected in series with the memristors of the IMPLY gate is included.

The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology, with several emerging applications including that of logic circuits. Several memristive logic families have been proposed, each with different attributes, in the current quest for energy-efficient computing systems of the future. However, limited endurance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation of such logic families. In this work we build upon a well-known accurate physics-based model of a bipolar metal-oxide resistive RAM device (supporting parasitics of the device structure and variability of switching voltages and resistance states) and use it to show how performance of memristor-based logic circuits can de degraded owing to both variability and state-drift impact. Based on previous work on CMOS-like memristive logic circuits, we propose a memristive ratioed logic scheme, which is crossbarcompatible, i.e. suitable for in-/near-memory computing, and tolerant to device variability, while also it does not affect the device endurance since computations do not involve switching the memristor states. As a figure of merit, we compare such new logic scheme with MAGIC, focusing on the universal NOR logic gate.

Memristors are being considered as promising devices for highly dense memory systems as well as the potential basis of new computational paradigms. In this scenario, and in relation with data processing, one of the more specific and differential logic functions is the material implication logic also named as IMPLY logic. Many papers have been published in this framework but few of them are related with experimental works using real memristor devices. In the paper authors show the verification of the IMPLY function by using Ni/HfO 2 /Si manufactured devices and laboratory measurements. The proper behavior of the IMPLY structure (2 memristors) has been shown. The paper also verifies the proper operation of a two-steps IMPLY-based NAND gate implementation, showing the electrical behavior of the circuit in a cycling operation. A new procedure to implement a NAND gate that requires only one step is experimentally shown as well.

Ever since the advent of the first TiO2-based memristor and the respective linear model published by Hewlett-Packard Labs, several behavioral models of memristors have been published. Such models capture the fundamental characteristics of resistive switching behavior through simple equations and rules, so they received a lot of attention and contributed significantly to the fast progress of research in this new and emerging device technology field. However, while this technology is maturing, accurate physicsbased models are being developed, which go deeper into the device dynamics and capture more details than what just would be the fundamentals: i.e. parasitics of the device structure, variability of threshold voltages and resistance states, temperature dependency, dynamic current fluctuations, etc. In this work we build upon such a physics-based model of a bipolar metal-oxide resistive RAM device, showing how to take into account device variability and its significance in evaluation of processing circuits. With the Cadence Virtuoso suite, we focus on a family of memristive logic gate implementations showing that read & write errors can emerge due to both variability and state-drift impact, features rarely seen so far in results shown in other relevant published works.

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