Variance mismatch: identifying random-test resistance in DSP datapaths

Goodby, L.; Orailoğlu, Alex

doi:10.1109/icassp.1996.550558

Cited by 7 publications

(8 citation statements)

References 10 publications

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“…depends on the system coefficients and the input to the system. While is time-varying, by rearranging (5), a timeinvariant upper bound on can be found [see (6) at the bottom of the page].…”

Section: Methodsmentioning

confidence: 99%

Concurrent test for digital linear systems

Bayraktaroglu

Orailoğlu

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Invariant-based concurrent test schemes can provide economical solutions to the problem of concurrent error detection. An invariant-based concurrent error-detection scheme for linear digital systems is proposed. The cost of concurrent error-detection hardware is appreciably reduced due to utilization of a time-extended invariant, which extends the error-checking computation over time and, thus, reduces hardware requirements. Error-detection capabilities of the scheme proposed in this work are analyzed and conditions on the implementation for achieving complete fault coverage are outlined. Implementations fulfilling such conditions have been shown through experiments to provide 100% concurrent fault detection.

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“…depends on the system coefficients and the input to the system. While is time-varying, by rearranging (5), a timeinvariant upper bound on can be found [see (6) at the bottom of the page].…”

Section: Methodsmentioning

confidence: 99%

Concurrent test for digital linear systems

Bayraktaroglu

Orailoğlu

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The test signal variance problem can be addressed by using a test signal with variance close to one, the upper limit on signal variance if the test signal is interpreted as a two's-complement number in the interval ; specific approaches are outlined in [23], [3], and [24]. One means of implementing a maximum-variance test signal is to simply use 1 bit of an LFSR to select between the maximum positive and minimum negative representable numbers.…”

Section: A Bist Test Pattern Generatormentioning

confidence: 99%

Redundancy and testability in digital filter datapaths

Goodby

Orailoğlu²

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Test issues in application-specific digital filter datapaths are investigated. It is found that such designs can contain hundreds of redundant faults, making it difficult to accurately determine fault coverage. Since these redundant faults tend to appear in the same general location as test-resistant faults, the presence of many redundant faults can hide significant untested faults despite high overall test coverage. Classes of redundant faults that arise in digital filter datapaths are described, and we propose a suite of techniques for identifying and eliminating the most common redundancies based on arithmetic optimization. The approach is suitable as a front-end to more accurate fault simulation, or can be used in the design process to eliminate redundant logic. The approach is validated as a tool for developing very high-coverage built-in self-test circuits, showing that 100% fault coverage can be achieved in 24k-gate filters with as little as 1% area overhead. When used as a datapath optimization technique, the average area reduction over 15 designs was 8.9%, compared with moderately optimized designs. As a front-end to fault simulation, the approach yielded a 97.9% average reduction in the number of undetected faults across the 15 designs.

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“…This is due to the fact that ABIST is not capable of activating the faults at the sign bit of most adders. These faults usually require high variance input patterns [4]. Therefore, a set of high variance patterns generated by the same off-line hardware with an increment of ½½½½½½¼½½½is applied in order to detect the remaining sign bit faults.…”

Section: Resultsmentioning

confidence: 99%

Unifying methodologies for high fault coverage concurrent and off-line test of digital filters

Bayraktaroglu

Orailoğlu²

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No

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A low-cost on-line test scheme for digital filters that additionally provides an off-line BIST solution is proposed. The scheme utilizes an invariant of the digital filter in order to detect on-line possible circuit malfunctions. The on-line checking hardware is shared with off-line BIST. The analysis performed indicates that exact 100% fault secureness is attained when the digital filter is designed according to design criteria that we identify in the paper. Furthermore, fault simulations show near 100% fault coverage for off-line BIST.

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Variance mismatch: identifying random-test resistance in DSP datapaths

Cited by 7 publications

References 10 publications

Concurrent test for digital linear systems

Concurrent test for digital linear systems

Redundancy and testability in digital filter datapaths

Unifying methodologies for high fault coverage concurrent and off-line test of digital filters

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