Variance Reduction and Outliers: Statistical Analysis of Semiconductor Test Data

Daasch, W.R.; Madge, R.

doi:10.1109/test.2005.1583988

Cited by 31 publications

(9 citation statements)

References 20 publications

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“…The performance is maximized when the number of active vectors is in the range of 10-50 for 64 IDDQ measurements. This performance level improves upon reported IDDQ statistical processing [5].…”

Section: Effectiveness Of Kendall τsupporting

confidence: 78%

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Application of non-parametric statistics of the parametric response for defect diagnosis

Gudavalli

Daasch

Nigh

et al. 2009

2009 International Test Conference

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This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses are correlated for same parametric tests at different conditions such as temperature, voltage and or other stress. Nonparametric correlation methods are used to calculate the intradie correlation. When intra-die correlation is found to be low the elevated vectors that lower correlation are extracted and input to IDDQ-based diagnostic tools. Monte-Carlo simulations are described to obtain confidence bounds of the correlation for good die test response.

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Section: Effectiveness Of Kendall τsupporting

confidence: 78%

“…Post-processing has been shown to work well at reducing variance although the methods continue to use the variance of all the measurements and Paper 1. 4 INTERNATIONAL TEST CONFERENCE not the variance of individual measurements [5]. The rank however, provides a per-vector view of the data.…”

Section: Correlation Model For Iddqmentioning

confidence: 99%

Application of non-parametric statistics of the parametric response for defect diagnosis

Gudavalli

Daasch

Nigh

et al. 2009

2009 International Test Conference

Self Cite

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“…Examples for Iddq are the ratio of maximum to minimum current ("current ratios" [31]), significant steps in the sorted currents ("current signatures", [16]) and changes in one vector to the next ("delta-I DDQ " [32]). Similar concepts were applied to MinV DD testing, where a predicted value of MinV DD was obtained from measurements of neighboring die and this value became the limit for the die under test [11].…”

Section: A Outlier Screens and Data Driven Testmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE.

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“…Larger values of these parameters result in a larger test set. In contrast to previous variation-aware test generation approaches [6][7][8][9][10][11][12], the proposed algorithm relies on accurate fault efficiencies of the generated test sets. For this reason, the algorithm employs a very recently introduced SAT-based test-generation engine WaveSAT [5] that works with waveform precision and does not rely on path sensitization.…”

Section: Introductionmentioning

confidence: 99%

Variation-aware deterministic ATPG

Sauer

Polian

Imhof

et al. 2014

2014 19th IEEE European Test Symposium (ETS)

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In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.

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Variance Reduction and Outliers: Statistical Analysis of Semiconductor Test Data

Cited by 31 publications

References 20 publications

Application of non-parametric statistics of the parametric response for defect diagnosis

Application of non-parametric statistics of the parametric response for defect diagnosis

Towards Variation-Aware Test Methods

Variation-aware deterministic ATPG

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