Variation-Aware Low-Power Buffer Design

Nicopoulos, Chrysostomos; Yanamandra, Aditya; Srinivasan, Suresh; Narayanan, Vijaykrishnan; Irwin, M.J.

doi:10.1109/acssc.2007.4487459

Cited by 8 publications

(6 citation statements)

References 6 publications

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“…To activate channels and lanes, ABNs with shallow router pipelines can either use predictors similar to non-drowsy SRAMs [33], or leave a small number of lanes constantly activated in order to better tolerate the activation delay of other lanes. In addition, ABNs have similar power gating granularity and therefore do not require more complicated power distribution networks or power gating transistors than multinets or other past work [26,38,12].…”

Section: Discussionmentioning

confidence: 99%

“…For example, channels can be activated or deactivated individually, and the network needs to activate channels in time for flit traversal or enable detours and guarantee full connectivity with inactive channels [32,45,46,8]. Power gating of input buffers is possible at the granularity of entire buffers [32,17], VCs [33], or individual buffer entries [26,38]. Power gating has also been applied to the switch and allocators [17,49].…”

Section: Background and Related Workmentioning

confidence: 99%

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Variable-width datapath for on-chip network static power reduction

Shalf

2014

2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

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Section: Discussionmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

Variable-width datapath for on-chip network static power reduction

Shalf

2014

2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

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“…Several features of ViCHaR have encouraged some other researchers to employ it in their designs. Nicopoulos et al [12] presented the design of an intelligent buffer that logically reorders the entries in an FIFO buffer to minimize the leakage power. In this design, the BSs are first classified on the basis of their leakage characteristics.…”

Section: Previous Research Workmentioning

confidence: 99%

Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

Oveis-Gharan

Khan

2016

IEEE Trans. VLSI Syst.

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The number of cores on a chip is rapidly increased the on chip need an efficient communication structure as network on chip (NoC). The channel buffer organization of NoC uses virtual channels (VCs) to improve data flow and performance of the NoC system. Dynamically allocated multi queues are an good mechanism to reach VC flow control with maximum no of buffer utilization. In this design, VCs employ variable number of buffer slots depending on the network traffic. we propose a new input port micro architecture to cooperate our efficient dynamic VC (EDVC) approach that is built on DAMQ buffers. To show the advantages of EDVC, we compare its micro-architecture with that of the traditional dynamic VC (CDVC), it's also employs link-list tables for buffer organization. In terms an hardware, EDVC input-port organization consumes on average 51% less power for ASIC design when compared with the CDVC input port. The saving is even good when compared with VC regulator methodology. This EDVC approach can improve NoC latency by 38%-48% and throughput by 100% on average as compared with the CDVC mechanism. The proposed design parameters are analyzed using Xilinx 9.1.

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“…A few interesting features of ViChaR architecture has encouraged some researchers to employ it in their designs. The design of an intelligent buffer that logically reorders the entries in FIFO buffer to minimize overall leakage power consumption is presented by Nicopoulos et al [21]. They employ the ViChaR [2] concept to design their buffer architecture, called IntelliBuffer.…”

Section: Previous Research Workmentioning

confidence: 99%

Packet-based Adaptive Virtual Channel Configuration for NoC Systems

Gharan¹

2015

IJCDS

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The escalating numbers of on-chip processing cores necessitate the introduction of a high performance and scalable communication backbone. In respond to this, Network on Chip (NoC) systems are introduced to play an important role in determining the performance and power of the entire chip. Specifically, Packet-based NoC is known as the most viable communication solution for the multi-core SoC of the future. In NoC design, the buffering organization directs the control of data flow as well as facilitates the use of Virtual Channels (VC). In terms of buffering, the VC mechanism is categorized into static and dynamic models. In dynamic VC mechanism, VCs employ a variable number of buffer slots according to the on-chip traffic. This feature of dynamic VC mechanism encourages us to introduce the Packet Based Virtual Channel (PBVC) approach. The idea is that a VC is reserved when a packet comes in a router, and released when the packet leaves the router. This prevents a VC to hold more than one packet that subsequently removes the Head-of-Line (HOL) blocking in NoCs. Our proposed technique is more suitable for dynamically allocated multi-queue (DAMQ) schemes. In these schemes, an input or output port comprises a centralized buffer whose slots are dynamically allocated to VCs in real-time and according to the traffic conditions. We introduce the architectural and structural details of our DAMQ buffer organization as well as the hardware that our approach imposes. The simulation results support the theoretical concepts of our proposed technique. The results of the hardware requirements for the proposed model are compared with the conventional models. The experimental results show that PBVC can improve the network latency by 40% and the network throughput by 23% on average as compared to the conventional designs for specific high HOL traffic.

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Variation-Aware Low-Power Buffer Design

Cited by 8 publications

References 6 publications

Variable-width datapath for on-chip network static power reduction

Variable-width datapath for on-chip network static power reduction

Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

Packet-based Adaptive Virtual Channel Configuration for NoC Systems

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