Variation in natural threshold voltage of NVM circuits due to dopant fluctuations and its impact on reliability

Burnett, D.; Higman, J.M.; Hoefler, A.; Li, C.-N.B.; Kuhn, P.

doi:10.1109/iedm.2002.1175896

Cited by 7 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, sustaining Moore's law through technology scaling into the nanoscale regime poses several challenges. Chief among these are the hurdles introduced by noise [Kish 2002;Natori et al 1998], parameter variations [Borkar et al 2003], dopant concentration [Burnett et al 2002], etc. Among the challenges posed by statistical behaviors, noise is a fundamental limit for continuing transistor scaling.…”

Section: Introductionmentioning

confidence: 99%

Models for characterizing noise based PCMOS circuits

Singh

Basu

Ling

et al. 2013

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

Quick and accurate error-rate prediction of Probabilistic CMOS (PCMOS) circuits is crucial for their systematic design and performance evaluation. While still in the early stage of research, PCMOS has shown potential to drastically reduce energy consumption at a cost of increased errors. Recently, a methodology has been proposed which could predict the error rates of cascade structures of blocks in PCMOS. This methodology requires error rates of unique blocks to predict the error rates of multiblock cascade structures composed of these unique blocks. In this article we present a new model for characterization of probabilistic circuits/blocks and present a procedure to find and characterize unique circuits/blocks. Unlike prior approaches, our new model distinguishes distinct filtering effects per output, thereby improving prediction accuracy by an average of 95% over the prior art by Palem and coauthors. Furthermore, we show two models where our new model with three stages is 18% more accurate, on average, than our simpler two-stage model. We apply our proposed models to Ripple Carry Adders and Wallace Tree Multipliers and show that using our models, the methodology of cascade structures can predict error rates of PCMOS circuits with reasonable accuracy (within 9%) in PCMOS for uniform voltages as well as multiple voltages. Finally, our approach takes seconds of simulation time whereas using HSPICE would take days of simulation time.

show abstract

Section: Introductionmentioning

confidence: 99%

Models for characterizing noise based PCMOS circuits

Singh

Basu

Ling

et al. 2013

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…Moreover, these devices do not suffer of drain turn-on effect [3], allowing for cell length scaling and high reading drain voltage. In conventional FG devices, the intra-die variation of natural threshold voltage, due to dopant fluctuations of the well doping, has been ascribed as a major reliability concern as devices continue to scale [4].…”

Section: Introductionmentioning

confidence: 99%

Modeling of the programming window distribution in multinanocrystals memories

Perniola

Salvo

Ghibaudo

et al. 2003

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

In this paper, the impact of the Si nanocrystals technological fluctuations on the programming window dispersion of multi nanocrystals memory is thoroughly investigated. Techno-logical dispersions of different nanocrystals populations, directly measured by high-resolution transmission electron microscopy, are used as starting points for the modeling of the device charac-teristics. Numerical Monte Carlo simulations as well as an original compact modeling, based on the compound distributions (CD) statistics, are here presented. Exact analytical results (CD model), approximated analytical results (CD+Central Limit Theorem model) and numerical results (numerical convolution) are deeply discussed. Finally, the good agreement between our simulations and experimental data of ultrascaled nanocrystal devices, made by conventional UV lithography or by e-beam lithography, definitively confirms the validity of our theoretical approach.

show abstract

“…Large SRAM arrays are especially vulnerable to variation at low V dd [1,6,7,25,41]. They are optimized for area and power and therefore built using the smallest transistors, which are the most affected by random variation.…”

Section: Near Threshold Computingmentioning

confidence: 99%